Freescale Semiconductor	MSEPFR4310MPB40_1M63J
Mask Set Errata	Rev. August 12, 2008

PFR4310MPB40, Mask 1M63J

Introduction

This errata sheet applies to the following devices:

PFR4310MPB40

MCU Device Mask Set Identification

The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1K79X. All standard devices are marked with a mask set number and a date code.

MCU Device Date Codes

Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002.

MCU Device Part Number Prefixes

Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix.

Errata System Tracking Numbers

MUCtsXXXXX is the tracking number for device errata. It can be used with the mask set and date code to identify a specific erratum.

Errata Summary

Errata Number	Module affected	Brief Description	Work- around
MUCts03599	clk_div	CLKOUT can remain at "1" after external reset with CLK_S[1:0] set to "11"	NO
MUCts03768	flexray_ipi	Read-only bits in PIER1 register can also be written	YES
MUCts03975	crg_mfr4300	External Clock Mode and External Host Interface may be selected incorrectly after power up	YES

CLKOUT can remain at "1" after external reset with CLK_S[1:0] set to "11"

MUCts03599

Description

During the external reset sequence, the CRG block latches the values on

CLK_S[1:0]. 

The data sheet specifies that, if the latched values of CLK_S[1:0] =

"11", CLKOUT is disabled and is equal to "0". However, CLKOUT can remain

at "1" while disabled, if the following conditions are all true:

- CLKOUT was not disabled (i.e. was running), or was already disabled

and set to "1" prior to the current external reset.

- An external reset is applied.

- During the external reset sequence, the CLK_S[1:0] inputs are set to

"11" to disable CLKOUT.

- When the CRG latched the CLK_S[1:0] values, CLKOUT was "1".

Workaround

There is no workaround.

Read-only bits in PIER1 register can also be written

MUCts03768

Description

Bits 0, 1, 2, 3, 6, and 7 are described in the MFR4310 Reference Manuals

as "read-only". However, these bits actually behave as "read/write"

bits, and can be modified by writing to them.

Workaround

When writing to the PIER1 register, always write zeros to these bit

locations.

External Clock Mode and External Host Interface may be selected incorrectly after power up

MUCts03975

Description

After applying power to the device, it may happen that the External

Clock Mode and the External Host Interface are not set according to the

settings of the pins CLK_S0 and CLK_S1 for the External Clock, and

IF_SEL0 and IF_SEL1 for the External Host Interface. In this case, the

CLKOUT output pin remains "0" and no host interface is selected, which

prevents the host from accessing the device internal registers.

Workaround

The application should generate an additional hardware reset pulse via

the RESET pin at least 1ms after applying power to the device.



This additional external reset triggers the correct selection of the

External Clock Mode and External Host Interface.