ࡱ>   Root Entry xCache  Cells ssParts ss OrCAD Windows Library gQOQ"Arial+x BlockModify1Courier New1ST PART FIELD2ND PART FIELD3RD PART FIELD4TH PART FIELD5TH PART FIELD6TH PART FIELD7TH PART FIELD PCB Footprintddd00Views ssLibrary6Symbolsspv$Types$CLASSICPart ReferenceValueOQMKL15Z128VLK4_80PkOQMKL15Z128VLK4_80P.NormalkOQOQOQGraphics spv$Types$PackagesspvExportBlocks ssCells Directory  0Parts Directory   7Views Directory  NetBundleMapData"  Symbols Directory$Graphics Directory&Packages Directory&0ExportBlocks Directory.OQMKL15Z128VLK4_80PkOQMKL15Z128VLK4_80P$ Q+ \9MKL15Z128VLK4_80PMKL15Z128VLK4_80P.NormalA){:\9MKL15Z128VLK4_80P.Normal0(( bbPS \9PTA0/SWD_CLK/TSI0_CH1/TPM0_CH522!L1VLKT \9PTA1/TSI0_CH2/UART0_RX/TPM2_CH0<<!L1VLKC \9PTA12/TPM1_CH0nn!L1VLKC \9PTA13/TPM1_CH1xx!)M \9PTA14/SPI0_PCS0/UART0_TX!L \9PTA15/SPI0_SCK/UART0_RX!L1VLKN \9PTA16/SPI0_MOSI/SPI0_MISO!L1VLKN \9PTA17/SPI0_MISO/SPI0_MOSI!U \9 PTA18/EXTAL0/UART1_RX/TPM_CLKIN0!L1VLK` \9+PTA19/XTAL0/UART1_TX/TPM_CLKIN1/LPTMR0_ALT1!L1VLKe \90PTB0/LLWU_P5/ADC0_SE8/TSI0_CH0/I2C0_SCL/TPM1_CH0!L1VLK] \9(PTB1/ADC0_SE9/TSI0_CH6/I2C0_SDA/TPM1_CH1!L1VLKD \9PTB10/SPI1_PCS0!L1VLKC \9PTB11/SPI1_SCK!L1VLKk \96PTB16/TSI0_CH9/SPI1_MOSI/UART0_RX/TPM_CLKIN0/SPI1_MISO""!L1VLKl \97PTB17/TSI0_CH10/SPI1_MISO/UART0_TX/TPM_CLKIN1/SPI1_MOSI,,!L1VLKM \9PTB18/TSI0_CH11/TPM2_CH066!M \9PTB19/TSI0_CH12/TPM2_CH1@@!L1VLK_ \9*PTC0/ADC0_SE14/TSI0_CH13/EXTRG_IN/CMP0_OUT^^!tcamiq \9<PTC1/LLWU_P6/RTC_CLKIN/ADC0_SE15/TSI0_CH14/I2C1_SCL/TPM0_CH0hh!L1VLKC \9PTC10/I2C1_SCL!C \9PTC11/I2C1_SDA!L1VLKE \9PTC12/TPM_CLKIN0!E \9PTC13/TPM_CLKIN1!No: \9PTC16!L1VLK: \9PTC17!L1VLK9 \9VDD1""!L1VLK9 \9VDD2,,!L1VLK9 \9VDD366!L1VLK9 \9VDDATT!L1VLK: \9VREFHhh!NoL \9PTD0/SPI0_PCS0/TPM0_CH0b22!U \9 PTD1/ADC0_SE5B/SPI0_SCK/TPM0_CH1b<<!L1VLK_ \9*PTD2/SPI0_MOSI/UART2_RX/TPM0_CH2/SPI0_MISObFF!_ \9*PTD3/SPI0_MISO/UART2_TX/TPM0_CH3/SPI0_MOSIbPP!^ \9)PTD4/LLWU_P14/SPI1_PCS0/UART2_RX/TPM0_CH4bZZ!L1VLK^ \9)PTD5/ADC0_SE6B/SPI1_SCK/UART2_TX/TPM0_CH5bdd!i \94PTD6/LLWU_P15/ADC0_SE7B/SPI1_MOSI/UART0_RX/SPI1_MISObnn!L1VLKV \9!PTD7/SPI1_MISO/UART0_TX/SPI1_MOSIbxx!L1VLK^ \9)PTB2/ADC0_SE12/TSI0_CH7/I2C0_SCL/TPM2_CH0!^ \9)PTB3/ADC0_SE13/TSI0_CH8/I2C0_SDA/TPM2_CH1!B \9 PTB8/EXTRG_IN!+x9 \9PTB9!L1VLK_ \9*PTC2/ADC0_SE11/TSI0_CH15/I2C1_SDA/TPM0_CH1rr!Z \9%PTC3/LLWU_P7/UART1_RX/TPM0_CH2/CLKOUT||!L1VLK] \9(PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/TPM0_CH3!_ \9*PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT!h \93PTC6/LLWU_P10/CMP0_IN0/SPI0_MOSI/EXTRG_IN/SPI0_MISO!V \9!PTC7/CMP0_IN1/SPI0_MISO/SPI0_MOSI!T \9PTC8/CMP0_IN2/I2C0_SCL/TPM0_CH4!T \9PTC9/CMP0_IN3/I2C0_SDA/TPM0_CH5!No9 \9VSS166:!9 \9VSS2,,:!9 \9VSS3"":!L1VLK9 \9VSSATT:!L1VLK: \9VREFLhh:!L1VLK_ \9*PTE0/UART1_TX/RTC_CLKOUT/CMP0_OUT/I2C1_SDAb!_ \9*PTE1/SPI1_MOSI/UART1_RX/SPI1_MISO/I2C1_SCLb!L1VLKj \95PTE16/ADC0_DP1/ADC0_SE1/SPI0_PCS0/UART2_TX/TPM_CLKIN0b!L1VLKv \9APTE17/ADC0_DM1/ADC0_SE5A/SPI0_SCK/UART2_RX/TPM_CLKIN1/LPTMR0_ALT3b!i \94PTE18/ADC0_DP2/ADC0_SE2/SPI0_MOSI/I2C0_SDA/SPI0_MISOb!L1VLKj \95PTE19/ADC0_DM2/ADC0_SE6A/SPI0_MISO/I2C0_SCL/SPI0_MOSIb!^ \9)PTE20/ADC0_DP0/ADC0_SE0/TPM1_CH0/UART0_TXb!L1VLK_ \9*PTE21/ADC0_DM0/ADC0_SE4A/TPM1_CH1/UART0_RXb!^ \9)PTE22/ADC0_DP3/ADC0_SE3/TPM2_CH0/UART2_TXb!0_TPM_ \9*PTE23/ADC0_DM3/ADC0_SE7A/TPM2_CH1/UART2_RXb""!0_PM2L \9PTE24/TPM0_CH0/I2C0_SCLb,,!L \9PTE25/TPM0_CH1/I2C0_SDAb66!L1VLKa \9,PTE29/CMP0_IN5/ADC0_SE4B/TPM0_CH2/TPM_CLKIN0b@@!j \95PTE30/DAC0_OUT/ADC0_SE23/CMP0_IN4/TPM0_CH3/TPM_CLKIN1bJJ!C \9PTE31/TPM0_CH4bTT!INontB \9 PTE2/SPI1_SCKb!M \9PTE3/SPI1_MISO/SPI1_MOSIb!C \9PTE4/SPI1_PCS0b!L1VLK9 \9PTE5b!#T \9PTA2/TSI0_CH3/UART0_TX/TPM2_CH1FF!\ \9'PTA3/SWD_DIO/TSI0_CH4/I2C1_SCL/TPM0_CH0PP!tpion[ \9&PTA4/N\M\I\/TSI0_CH5/I2C1_SDA/TPM0_CH1ZZ!B \9 PTA5/TPM0_CH2dd!L1VLKE \9PTA20/R\E\S\E\T\!'"' '\90'"' '\9:&0ZUM+ \9MKL15Z128VLK4_80PU  \9MKL15Z128VLK4_80PP2627323334353637404143444950515253545556676869707172738601718737475767778798045464748575861626364656683959201912910111213141516242521222334562829303142