201908004I : i.MXRT1060 & i.MXRT1064 Errata Rev1 Updates
NXP Semiconductors announces errata update for the i.MXRT1060 & i.MXRT1064 to revision 1. The revision history included in the updated documents provides a detailed description of the changes. Changes are summarized below.Added following 5 errata:* ERR011572: Cortex-M7: Write-Trough stores and loads may return incorrect data* ERR050130: PIT: Temporary incorrect value reported in LMTR64H register in lifetimer mode* ERR050144: SAI: Setting FCONT = 1 when TMR > 0 may not function correctly* ERR050101: USB: Endpoint conflict issue in device mode* ERR050194: QTMR: overflow flag and interrupt can't be generated while configured as counter up modeThe i.MXRT1060 & i.MXRT1064 errata revision 1 is attached to this notice and can be found at:https://www.nxp.com/docs/en/nxp/errata/IMXRT1060CE.pdfhttps://www.nxp.com/docs/en/errata/IMXRT1064CE.pdf
| PCNタイプ | カテゴリー変更 | 発行日 | 有効期限 |
|---|---|---|---|
| Customer Information Notification | Errata | 10-Sep-2019 | 11-Sep-2019 |
変更理由
The errata were added for additional technical clarification on some device features.
対象製品の特定について
Product identification does not change
予想される影響
No impact on form fit function reliability or quality.
対象品番
| 品番／12NC | 最終購入日 | 最終納品日 | 交換品番 |
|---|---|---|---|
|
MIMXRT1061CVJ5A (935379986557) |
- | - | - |
|
MIMXRT1061CVL5A (935373201557) |
- | - | - |
|
MIMXRT1061DVJ6A (935386102557) |
- | - | - |
|
MIMXRT1061DVL6A (935373202557) |
- | - | - |
|
MIMXRT1062CVJ5A (935379987557) |
- | - | - |
|
MIMXRT1062CVL5A (935373203557) |
- | - | - |
|
MIMXRT1062DVJ6A (935379988557) |
- | - | - |
|
MIMXRT1062DVL6A (935373204557) |
- | - | - |
|
MIMXRT1064CVL5A (935377468557) |
- | - | - |
|
MIMXRT1064DVL6A (935377469557) |
- | - | - |
|
MIMXRT1064DVL6AR (935377469518) |
- | - | - |