80C51 8-Bit Microcontroller Family

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製品詳細

ブロック図

Block diagram: P87C51RA2BA, P87C51RA2FA, P87C51RB2BA, P87C51RB2BBD, P87C51RB2BN

Block diagram: P87C51RA2BA, P87C51RA2FA, P87C51RB2BA, P87C51RB2BBD, P87C51RB2BN, P87C51RB2FA, P87C51RC2BBD, P87C51RC2BN, P87C51RC2FA, P87C51RC2FN, P87C51RD2BA, P87C51RD2BBD, P87C51RD2FA, P87C51RD2FBD, P87C660X2BBD, P87C660X2FA

Features

  • 80C51 Central Processing Unit
    • 8 kbytes OTP (87C51RA2)
    • 16 kbytes OTP (87C51RB2)
    • 32 kbytes OTP (87C51RC2)
    • 64 kbytes OTP (87C51RD2)
    • 512 byte RAM (87C51RA2/RB2/RC2)
    • 1 kbyte RAM (87C51RD2)
    • Boolean processor
    • Fully static operation
    • Low voltage (2.7 V to 5.5 V at 16 MHz) operation
  • 12-clock operation with selectable 6-clock operation (via software or via parallel programmer)
  • Memory addressing capability
    • Up to 64 kbytes ROM and 64 kbytes RAM
  • Power control modes:
    • Clock can be stopped and resumed
    • Idle mode
    • Power-down mode
  • CMOS and TTL compatible
  • Two speed ranges at V CC = 5 V
    • 0 to 30 MHz with 6-clock operation
    • 0 to 33 MHz with 12-clock operation
  • Parallel programming with 87C51 compatible hardware interface to programmer
  • RAM expandable externally to 64 kbytes
  • Programmable Counter Array (PCA)
    • PWM
    • Capture/compare
  • PLCC, LQFP, or DIP package
  • Extended temperature ranges
  • Dual Data Pointers
  • Security bits (3 bits)
  • Encryption array - 64 bytes
  • Seven interrupt sources
  • 4 interrupt priority levels
  • Four 8-bit I/O ports
  • Full-duplex enhanced UART
    • Framing error detection
    • Automatic address recognition
  • Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)
  • Programmable clock-out pin
  • Asynchronous port reset
  • Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock mode)
  • Wake-up from Power Down by an external interrupt

部品番号: P87C51RD2BBD.

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