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Parallel Bus to 1 Channel Fm+ I2C-Bus Controller
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PCA9661B device is "Not recommended for new designs", please use the replacement part PCA9665APW
The PCA9661 is an advanced single leader mode I²C-bus controller. It is a fourth generation bus controller designed for data intensive I²C-bus data transfers. It has one I²C-bus channel with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology. The serial channel has a generous 4352 byte data buffer which makes the PCA9661 the ideal companion to any CPU that needs to transmit and receive large amounts of serial data with minimal interruptions.
The PCA9661 is a 8-bit parallel-bus to I²C-bus protocol converter. It can be configured to communicate with up to 64 followers in one serial sequence with no intervention from the CPU. The controller also has a sequence loop control feature that allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I²C-bus and for the interval timer used in sequence looping. This feature greatly reduces CPU overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger signal controls the rate at which a stored sequence is re-transmitted over the I²C-bus.
Error reporting is handled at the transaction level, channel level, and controller level. A simple interrupt tree and interrupt masks allow further customization of interrupt management.
The controller parallel bus interface runs at 3.3 V and the I²C-bus I/Os logic levels are referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.
Outline 3d SOT313-2
製品詳細
Features
Key Features
- Parallel-bus to I²C-bus protocol converter and interface
- 1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
- Internal oscillator trimmed to 1 % accuracy reduces external components
- 4352-byte buffer for the Fm+ channel
- Communicates with up to 64 followers in one serial sequence
- Sequence looping with interval timer
- Supports SCL clock stretching
- JTAG port available for boundary scan testing during board manufacturing process
- Trigger input synchronizes serial communication exactly with external events
- Maskable interrupts
- Fast-mode Plus I²C-bus capable and compatible with SMBus
3 Reset Levels
- Individual software channel reset
- Global software reset
- Global hardware RESET pin
Operating Supply Voltage
- 3.0 V to 3.6 V (device and host interface)
I²C-Bus I/O Supply Voltage
- 3.0 V to 5.5 V
Latch-Up Testing
- Done to JEDEC Standard JESD78, which exceeds 100 mA
ESD Protection
- Exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
Packages
- LQFP48
ドキュメント
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