Using NPUs to Increase Performance and Power Efficiency of ML Applications | NXP Semiconductors

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Using NPUs to Increase Performance and Power Efficiency of ML Applications

Using NPUs to Increase Performance and Power Efficiency of ML Applications

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About This Training

Market demands for user privacy and security, along with a need for lower latency, are pushing more and more processing capability to the edge. The increasing prevalence of ML in industrial and IoT edge applications is driving demand for higher performance in embedded devices within the power constraints.

This presentation will explore the acceleration of machine learning on low power and resource-constrained embedded systems using the Arm Ethos-U65 microNPU. It will also show how an open source and collaborative software approach will enable developers to easily create and deploy ML applications.

Presentation

Using NPUs to Increase Performance and Power Efficiency of ML Applications

What You Will Learn

Discover why ML at the edge is important
Learn about new emerging hardware architectures for accelerating ML at the edge
Explore NXP software enablement to simplify implementation of ML

Presented by

Tanuj Arora
Product Manager, Ethos-U NPUs, Arm
Ben Eckermann
Chief Engineer of AI/ML Hardware, Edge Processing, NXP Semiconductors
Natraj Ekambaram
Director of AI/ML Software, Edge Processing, , NXP Semiconductors

期間

1 hr

言語

英語

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Additional Resources

eIQ^® ML Software Development Environment

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