Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
パッケージ
LBGA196: LBGA196, plastic, low profile ball grid array; 196 balls; 1 mm pitch; 15 mm x 15 mm x 1.16 mm body
購入オプション
DSP56303VF100
生産終了 (EOL)
12NC: 935309309557
詳細
注文
DSP56303VF100R2
製造中止
12NC: 935309309518
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | DSP56301PW100 |
| パラメータ | 値 |
|---|---|
Number of pins | 196 |
Package Style | LBGA |
環境
| Part/12NC | 鉛フリー | EU RoHS | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
DSP56303VF100(935309309557) | No | No |  | e0 | REACH SVHC | 614.0 |
DSP56303VF100R2(935309309518) | No | No | | e0 | REACH SVHC | 614.0 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 鉛はんだ | 鉛はんだ | 鉛はんだ | |||||
DSP56303VF100 (935309309557) | No | 3 | 220 | 30 | |||
DSP56303VF100R2 (935309309518) | No | 3 | 220 | 30 | |||
配送
| Part/12NC | 関税分類番号（米国)免責事項: | 輸出規制品目番号（米国） |
|---|---|---|
DSP56303VF100 (935309309557) | 854231 | 3A991A2 |
DSP56303VF100R2 (935309309518) | 854231 | 3A991A2 |
製造終了品・代替品データ
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
DSP56303VF100 (935309309557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
DSP56303VF100R2 (935309309518) | ||||
DSP56303VF100 (935309309557) | 2019-09-25 | 2019-09-26 | 201909022DN | Discontinuance Notice for DSP56303 68360 PBGA only 8569 P5020 8272 Family Lead only 8313 Family Lead only |
DSP56303VF100R2 (935309309518) | ||||
DSP56303VF100R2 (935309309518) | 2017-12-20 | 2018-01-03 | 201710023I | New PQ Label Input for Non-MPQ Shipments |
詳細 DSP56303
The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/fax processing, videoconferencing, audio applications, control, and general digital signal processing.
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single clock cycle per instruction engine providing a twofold performance increase over Our popular DSP56000 core family, while retaining code compatibility. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0-3.6 volts. The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products.
Archived content is no longer updated and is made available for historical reference only.