Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
QFP160: QFP160, plastic, quad flat package; 160 terminals; 0.65 mm pitch; 28 mm x 28 mm x 3.3 mm body
12NC: 935323991557
詳細
注文
パラメータ | 値 |
---|---|
Security Status | COMPANY PUBLIC |
Description | MCF5206 V2CORE 512SRAM |
パラメータ | 値 |
---|---|
Number of pins | 160 |
Package Style | QFP |
Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|---|
MCF5206AB25A(935323991557) | Yes | Yes Certificate Of Analysis (CoA) | No | e3 | REACH SVHC | 5566.8 |
Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
---|---|---|---|---|---|---|---|
鉛フリーはんだ | 鉛フリーはんだ | 鉛フリーはんだ | |||||
MCF5206AB25A (935323991557) | No | 3 | 245 | 30 |
Part/12NC | 関税分類番号(米国)免責事項: | 輸出規制品目番号(米国) |
---|---|---|
MCF5206AB25A (935323991557) | 854231 | 3A991A2 |
Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
---|---|---|---|---|
MCF5206AB25A (935323991557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
Archived content is no longer updated and is made available for historical reference only.
The MCF5206 integrated microprocessor combines a ColdFire® V2 processor core with peripheral functions such as a dynamic random accesss memory (DRAM) controller, timers, parallel and serial interfaces and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the on-chip instruction cache and static random access memory (SRAM) provide single-cycle access to critical code and data. The MCF5206 greatly reduces the time required for system design and implementation by packaging common system functions on-chip and providing glueless interfaces to 8-, 16-, and 32-bit DRAM, SRAM, ROM and input output (I/O) devices.