Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
購入オプション
P87C52SFAA,512
製造中止
12NC: 935252890512
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Product category | 230-OTP/ROM- |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
P87C52SFAA,512(935252890512) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 2353.33601512 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | フィット | MTBF | 投資家情報 | ||
|---|---|---|---|---|---|---|---|---|
| 鉛はんだ | 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||||
P87C52SFAA,512 (935252890512) | No | 3 | 3 | 225 | 245 | 2.84 | 2.58397932816537E8 | 0.0 |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
P87C52SFAA,512 (935252890512) | 854231 |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
P87C52SFAA,512 (935252890512) | - | 2016-06-30 | 2016-12-31 | None |
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
P87C52SFAA,512 (935252890512) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
詳細 P87C52SFAA
The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V.
The 8xC51 and 8xC52 contain a 128 bytes RAM and 256 bytes RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.
In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction-idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.