Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
購入オプション
P87C52X2FA,512
製造中止
12NC: 935269600512
詳細
注文
P87C52X2FA,529
製造中止
12NC: 935269600529
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Product category | 230-OTP/ROM- |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC |
|---|---|---|---|---|---|
P87C52X2FA,512(935269600512) | Yes | Yes | Yes |  | REACH SVHC |
P87C52X2FA,529(935269600529) | No | No | - | REACH SVHC |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | フィット | MTBF | 投資家情報 | ||
|---|---|---|---|---|---|---|---|---|
| 鉛はんだ | 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||||
P87C52X2FA,512 (935269600512) | No | 3 | 3 | 225 | 245 | 2.84 | 2.58397932816537E8 | 0.0 |
P87C52X2FA,529 (935269600529) | - | - | - | - | - | 2.84 | 2.58397932816537E8 | 0.0 |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
P87C52X2FA,512 (935269600512) | 854231 |
P87C52X2FA,529 (935269600529) | 854231 |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
P87C52X2FA,512 (935269600512) | - | 2016-06-30 | 2016-12-31 | None |
P87C52X2FA,529 (935269600529) | - | 2012-03-31 | 2012-06-30 | - |
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
P87C52X2FA,512 (935269600512) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
詳細 P87C52X2FA
The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs incorporating Philips? high-density CMOS technology with operation from 2.7 V to 5.5 V. They support both 6-clock and 12-clock operation.
The P8xC31X2/51X2 and P8xC32X2/52X2/54X2/58X2 contain 128 byte RAM and 256 byte RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.
In addition, the devices are low power static designs which offer a wide range of operating frequencies down to zero. Two software selectable modes of power reduction ? idle mode and power-down mode ? are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped.