Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
購入オプション
P87C552SFAA,512
製造中止
12NC: 935263958512
詳細
注文
P87C552SFAA,529
製造中止
12NC: 935263958529
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | 80C51 8-bit microcontroller |
Number of pins | 68 |
| パラメータ | 値 |
|---|---|
Package Style | PLCC |
Product category | 230-OTP/ROM- |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC |
|---|---|---|---|---|---|
P87C552SFAA,512(935263958512) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC |
P87C552SFAA,529(935263958529) | No | No | - | REACH SVHC |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | フィット | MTBF | 投資家情報 | ||
|---|---|---|---|---|---|---|---|---|
| 鉛はんだ | 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||||
P87C552SFAA,512 (935263958512) | No | 3 | 3 | 225 | 245 | 2.84 | 2.58397932816537E8 | 0.0 |
P87C552SFAA,529 (935263958529) | - | - | - | - | - | 2.84 | 2.58397932816537E8 | 0.0 |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
P87C552SFAA,512 (935263958512) | 854231 |
P87C552SFAA,529 (935263958529) | 854231 |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
P87C552SFAA,512 (935263958512) | - | 2004-12-31 | 2004-12-31 | None |
P87C552SFAA,529 (935263958529) | - | 2013-06-30 | 2013-12-31 | None |
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
P87C552SFAA,512 (935263958512) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
詳細 P87C552SFAA
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51.
The 87C552 contains a 8k ? 8 non-volatile EPROM, a 256 ? 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, four-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I 2C-bus), a ?watchdog? timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8xC552 can be expanded using standard TTL compatible memories and logic.
In addition, the 8xC552 has two software selectable modes of power reduction?idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. Optionally, the ADC can be operated in Idle mode. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal, 58pct of the instructions are executed in 0.75us and 40pct in 1.5us. Multiply and divide instructions require 3us.