Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
購入オプション
PCA9511AD,118
アクティブ
12NC: 935279307118
詳細
数量
単価
| 1 - 24 | $1.17 |
| 25 - 25 | $1.17 |
| 26 - 99 | $1.17 |
| 100+ | $1.17 |
注文
在庫あり:2,500
代理店からの注文操作機能
| パラメータ | 値 |
|---|---|
Operating Temperature (°C) | -40~85 |
I2C-bus (kHz) | 400 |
Operating voltage (VDC) | 2.7~5.5 |
| パラメータ | 値 |
|---|---|
Inputs | 1 |
Outputs | 1 |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
PCA9511AD,118(935279307118) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | REACH SVHC | 70.1936999999998 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | フィット | MTBF | 投資家情報 | ||
|---|---|---|---|---|---|---|---|---|
| 鉛はんだ | 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||||
PCA9511AD,118 (935279307118) | No | 1 | 1 | 240 | 260 | 2.0 | 5.0E8 | 0.0 |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
PCA9511AD,118 (935279307118) | 854239 |
詳細 PCA9511A
The PCA9511A is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip.