PCA9615DP 製品情報|NXP

購入オプション

PCA9615DPJ

製造中止

12NC: 935302505118

詳細

注文

操作機能

パラメータ
Inputs
1
Outputs
1
Type Of Offset
Static Offset
パラメータ
Supply Voltage [Min to Max] (V)
2.3 to 5.5, 3 to 5.5
Frequency (Max) (MHz)
1
Operating Temperature (Min-Max) (℃)
-40 to 85

環境

Part/12NC鉛フリーEU RoHSハロゲンフリーRHFインジケーターREACH SVHCWeight (mg)
PCA9615DPJ(935302505118)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
29.436000000000003
PCA9615DPZ(935302505431)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
29.436000000000003

品質

Part/12NC安全保障機能安全吸湿感度レベル (MSL)Peak Package Body Temperature (PPT) (C°)
鉛はんだ鉛フリーはんだ鉛はんだ鉛フリーはんだ
PCA9615DPJ
(935302505118)
No
1
1
240
260
PCA9615DPZ
(935302505431)
No
1
1
240
260

配送

Part/12NC関税分類番号(米国)免責事項:
PCA9615DPJ
(935302505118)
854239
PCA9615DPZ
(935302505431)
854239

製造終了品・代替品データ

Part/12NC製造終了のお知らせ最終購入日 最終納品日交換
PCA9615DPJ
(935302505118)
NOTICE
2022-02-26
2022-05-28
PCA9615DPZ
(935302505431)

製品変更のお知らせ

Part/12NC発行日有効期限PCNタイトル
PCA9615DPJ
(935302505118)
2021-10-052022-01-04202104008F01SOT552-1 Transfer from ATP-1 to ASEN
PCA9615DPZ
(935302505431)
PCA9615DPJ
(935302505118)
2021-06-192021-06-20202104010DNDiscontinuation R01 SOT552-1 Pack Method Change
PCA9615DPJ
(935302505118)
2021-05-24-202104008ASOT552-1 Transfer from ATP-1 to ASEN
PCA9615DPZ
(935302505431)

詳細 PCA9615DP

The PCA9615 is a Fast-mode Plus (Fm+) SMBus/I²C-bus buffer that extends the normal single-ended SMBus/I²C-bus through electrically noisy environments using a differential SMBus/I²C-bus (dI²C) physical layer, which is transparent to the SMBus/I²C-bus protocol layer. It consists of two single-ended to differential driver channels for the SCL (serial clock) and SDA (serial data).

The use of differential transmission lines between identical dI²C bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors.

The SMBus/I²C-bus was conceived as a simple slow speed digital link for short runs, typically on a single PCB or between adjacent PCBs with a common ground connection. Applications that extend the bus length or run long cables require careful design to preserve noise margin and reject interference.

The dI²C-bus buffers were designed to solve these problems and are ideally suited for rugged high noise environments and/or longer cable applications, allow multiple followers, and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least 3 meters (3 m), or longer cable runs at lower clock speeds. The dI²C-bus buffers are compatible with existing SMBus/I²C-bus devices and can drive Standard, Fast-mode, and Fast-mode Plus devices on the single-ended side.

Signal direction is automatic, and requires no external control. To prevent bus latch up, the standard SMBus/I²C-bus side of the bus buffer, the PCA9615 employs static offset, care should be taken when connecting these to other SMBus/I²C-bus buffers that may not operate with offset.

This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I²C-bus and the 4-wire dI²C-bus.

Additional circuitry allows the PCA9615 to be used for ‘hot swap’ applications, where systems are always on, but require insertion or removal of modules or cards without disruption to existing signals.

The PCA9615 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply, only serves as a reference and ranges from 2.3 V to 5.5 V. VDD(B), the line side supply, serves as the majority supply for circuitry and ranges from 3.0 V to 5.5 V.

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