PCF85162T 製品情報|NXP

購入オプション

PCF85162T/1Y

アクティブ

12NC: 935290708518

詳細

PCF85162T/1,118

製造中止

12NC: 935290708118

詳細

操作機能

パラメータ
Type Classification
LCD Segment Drivers
Max number of elements
128
Segments/elements of MUX 1:1
32
Segments/elements of MUX 1:2
64
Segments/elements of MUX 1:3
96
Segments/elements of MUX 1:4
128
I2C-bus
Y
VDD1 [min] (V)
1.8
パラメータ
VDD1 [max] (V)
5.5
VLCD [min] (V)
2.5
VLCD [max] (V)
6.5
ffr
77.0
Cascade for larger conf
Y
Failures in time
5
Mean time between failures
200000000

環境

Part/12NC鉛フリーEU RoHSハロゲンフリーRHFインジケーターREACH SVHCWeight (mg)
PCF85162T/1,118(935290708118)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
181.55
PCF85162T/1Y(935290708518)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
DREACH SVHC
181.55

品質

Part/12NC安全保障機能安全吸湿感度レベル (MSL)Peak Package Body Temperature (PPT) (C°)フィットMTBF
鉛はんだ鉛フリーはんだ鉛はんだ鉛フリーはんだ
PCF85162T/1,118
(935290708118)
No
1
1
240
260
5
2.0E8
PCF85162T/1Y
(935290708518)
No
3
3
240
260
5
2.0E8

配送

Part/12NC関税分類番号(米国)免責事項:
PCF85162T/1,118
(935290708118)
854239
PCF85162T/1Y
(935290708518)
854239

製造終了品・代替品データ

Part/12NC製造終了のお知らせ最終購入日 最終納品日交換
PCF85162T/1,118
(935290708118)
NOTICE
2021-09-01
2021-12-01
PCF85162T/1Y
(935290708518)

製品変更のお知らせ

Part/12NC発行日有効期限PCNタイトル
PCF85162T/1,118
(935290708118)
2021-08-112021-08-12202107021DNR01 - Discontinuation TSSOP48/56 for New Tape/Pack Method Release
PCF85162T/1,118
(935290708118)
2021-06-052021-10-01202102010F01Incorporation of Tape Holder for TSSOP48/TSSOP56 Assembly
PCF85162T/1,118
(935290708118)
2021-02-20-202102010AIncorporation of Tape Holder for TSSOP48/TSSOP56 Assembly

詳細 PCF85162T

The PCF85162 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. It can be easily cascaded for larger LCD applications. The PCF85162 is compatible with most microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes).