デザイン・ファイル
完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.
QorIQ® P3041 Quad-Core Communications Processors
- このページでは、新規設計を推奨しない製品に関する情報を掲載しています。
P3041 device is "Not recommended for new designs", please use the replacement families Power Architecture (T208x), Arm Architecture (LS1046, LS2080).
The QorIQ® P3041 processor is an optimized quad-core device that leverages architectural features pioneered in the P4 platform. Built on Power Architecture® technology, the P3041 fits into many of the same applications as the P4 platform processors, yet is designed to offer a more power- and cost-efficient solution.
The P3041 includes P4 platform features such as the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric which eliminates internal bottlenecks. This enables architectural compatibility from the P3041 to the P4 platform and also to the P5 platform, which uses the same architecture. P3041 is pin-compatible with P4040, P4080, P5010, and P5020.
製品詳細
Features
Core Complex
- Four high-performance e500mc cores up to 1.5 GHz
- Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 1 MB shared CorNet platform cache
Networking Elements
- One 10 Gbps Ethernet (XAUI) controllers
- Five 1 Gbps Ethernet controllers available on SGMII, 2.5 Gbps SGMII, or RGMII
Accelerators and Memory Control
- 64-bit (72-bit with ECC) DDR2/3 memory controller up to 1.3 GHz data rate
- DPAA incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Encryption (SEC 4.2)
- RegEx Pattern Matching (PME 2.1)
Basic Peripherals and Interconnect
- High-speed peripheral interfaces:
- Four PCI Express® v2.0 controllers/ports running at up to 5 GHz
- Two Serial RapidIO® 1.3/2.1 controllers/ports running at up to 5 GHz, with Type 9 and 11 messaging
- Two SATA 2.0 interfaces
- Two USB 2.0 controllers with integrated PHY, enhanced local bus controller (eLBC), SD/MMC, serial peripheral interface (SPI) controller, four I²C controllers, two dual
Additional Features
- Hardware hypervisor for safe partitioning of operating systems between cores
- Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
- Pin-and software-compatible with P4040, P4080, P5010, and P5020
比較表
| P2040 | P2041 | P3041 | |
|---|---|---|---|
| Cores | 4x e500mc | 4x e500mc | 4x e500mc |
| Core Frequency | 667 - 1200 MHz | 1200 - 1500 MHz | 1200 - 1500 MHz |
| L2 Cache | - | 128KB/Core | 128KB/Core |
| CoreNet Platform Cache | 1MB Frontside | 1MB Frontside | 1MB Frontside |
| DDR | 1x 64-bit DDR3/3L | 1x 64-bit DDR3/3L | 1x 64-bit DDR3/3L |
| GbE | 5 x 1 GbE | 5 x 1 GbE + 1 x 10 GbE | 5 x 1 GbE + 1 x 10 GbE |
| PCIe Gen 2.0 | 3x Gen 2.0 controllers 5.0GHz | 3x Gen 2.0 controllers 5.0GHz | 4x Gen 2.0 controllers 5.0GHz |
| USB 2.0 | 2 | 2 | 2 |
| sRIO 1.2 | 2 | 2 | 2 |
| Other Interfaces | 2 x SATA, 2 x 4-ch DMA engines, 4 x 2-pin UARTs or 2 x 4-pin UARTs | 2 x SATA, 2 x 4-ch DMA engines, 4 x 2-pin UARTs or 2 x 4-pin UARTs | 2 x SATA, 2 x 4-ch DMA engines, 4 x 2-pin UARTs or 2 x 4-pin UARTs |
| Accelerators | SEC4.2, PME 2.0 | SEC4.2, PME 2.0 | SEC4.2, PME 2.0 |
購入/パラメータ
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ドキュメント
クイック・リファレンス ドキュメンテーションの種類.
1-5 の 44 ドキュメント
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ファクト・シート
QorIQ P3041 - Fact Sheet注目
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ファクト・シート
P3041 Development System注目
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ホワイト・ペーパ
Secure Boot - White Paper注目
設計・リソース
ソフトウェア
クイック・リファレンス ソフトウェア・タイプ.
4 ソフトウェア・ファイル
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開発IDEと構築ツール
CodeWarrior Development Studio v10 for Power Architecture® Technology (Eclipse) EVAL注目
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BSPとデバイスドライバ
Linux® SDK for QorIQ® Processors
注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。