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1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
- このページには、製造中止（生産終了）となった製品の情報が記載されています。本ページに記載されている仕様および情報は、過去の参考情報です。
The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.
製品詳細
部品番号： SSTUM32868ET.
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ドキュメント
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