Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
- 製造終了
- SSTUM32868ET
購入オプション
SSTUM32868ET,518
製造中止
12NC: 935282729518
詳細
注文
SSTUM32868ET/S,518
製造中止
12NC: 935283146518
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Security Status | COMPANY PUBLIC |
Function | Latches/registered drivers |
Description | 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications |
| パラメータ | 値 |
|---|---|
Number of pins | 176 |
Package Style | TFBGA |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|
SSTUM32868ET,518(935282729518) | Yes | Yes | Yes |  | REACH SVHC | 222.814 |
SSTUM32868ET/S,518(935283146518) | Yes | Yes | Yes | | REACH SVHC | 220.0 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
|---|---|---|---|---|---|
| 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||
SSTUM32868ET,518 (935282729518) | No | 2 | 240 | 260 | |
SSTUM32868ET/S,518 (935283146518) | - | 2 | 240 | 260 | |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
SSTUM32868ET,518 (935282729518) | 854239 |
SSTUM32868ET/S,518 (935283146518) | 854239 |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
SSTUM32868ET,518 (935282729518) | - | 2013-06-30 | 2013-12-31 | None |
SSTUM32868ET/S,518 (935283146518) | - | 1998-01-30 | 1998-12-31 | SSTUM32868ET,518 (935282729518) |
詳細 SSTUM32868ET
Archived content is no longer updated and is made available for historical reference only.
The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.
The SSTUM32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. Finally, the SSTUM32868 is optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUM32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.