MPC853TVR100A 製品情報|NXP

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MPC853TVR100A

生産終了 (EOL)

12NC: 935324113557

詳細

注文

操作機能

パラメータ
Core Type
MPC8xx
Operating Frequency [Max] (MHz)
100
Core: Number of cores (SPEC)
1
パラメータ
External Memory Supported
EPROM, SRAM
Ambient Operating Temperature (Min to Max) (℃)
0 to 95

環境

Part/12NC鉛フリーEU RoHSハロゲンフリーRHFインジケーター2次インターコネクトREACH SVHCWeight (mg)
MPC853TVR100A(935324113557)
Yes
Yes
Certificate Of Analysis (CoA)
Yes
D
e1
REACH SVHC
1662.95

品質

Part/12NC安全保障機能安全吸湿感度レベル (MSL)Peak Package Body Temperature (PPT) (C°)Maximum Time at Peak Temperatures (s)
鉛フリーはんだ鉛フリーはんだ鉛フリーはんだ
MPC853TVR100A
(935324113557)
No
3
245
30

配送

Part/12NC関税分類番号(米国)免責事項:輸出規制品目番号(米国)
MPC853TVR100A
(935324113557)
854231
3A991A2

製造終了品・代替品データ

Part/12NC製造終了のお知らせ最終購入日 最終納品日交換
MPC853TVR100A
(935324113557)
NOTICE
2020-05-19
2020-11-19
-

製品変更のお知らせ

Part/12NC発行日有効期限PCNタイトル
MPC853TVR100A
(935324113557)
2020-12-152020-12-16202011011INXP Will Add a Sealed Date to the Product Label
MPC853TVR100A
(935324113557)
2019-11-182019-11-19201911010DNMPC866/859/852 and MPC885/880/875/870 Discontinuance
MPC853TVR100A
(935324113557)
2017-12-202018-01-03201710023INew PQ Label Input for Non-MPQ Shipments

詳細 MPC853T

The MPC853T is an "ethernet-only" member of the MPC866 Family. Like the MPC866, the MPC853T is a 0.18 micron version of the PowerQUICC® Family and can operate up to a maximum of 100 MHz on the MPC8xx Core with a maximum of 66 MHz external bus. The MPC853T has a 1.8 V core and has a 3.3 V I/O operation with 5 V TTL compatibilty. The MPC853T Integrated Communications Controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. The MPC853T is ideal for voice-enabled systems (TDM-based) and ethernet to ethernet applications such as line cards.

The MPC853T is a Power Architecture-based derivative of NXP® Semiconductors's Quad Integrated Communications Controller (PowerQUICC).. The CPU on the MPC853T is the MPC8xx core, a 32-bit microprocessor built on Power Architecture technology, incorporating memory management units (MMUs) and instruction and data caches.

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