Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
パッケージ
FBGA457: FBGA457, plastic, fine-pitch ball grid array; 457 balls; 0.8 mm pitch; 19 mm x 19 mm x 1.55 mm body
購入オプション
P1017NSN5HFB
生産終了 (EOL)
12NC: 935319815557
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Security Status | COMPANY PUBLIC |
Description | QorIQ, Power Architecture SoC, 800MHz, DDR3/3L, GbE, PCIe, USB, 0 to 105C, Rev 1.1 |
| パラメータ | 値 |
|---|---|
Number of pins | 457 |
Package Style | FBGA |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|---|
P1017NSN5HFB(935319815557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e2 | REACH SVHC | 991.1 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 鉛フリーはんだ | 鉛フリーはんだ | 鉛フリーはんだ | |||||
P1017NSN5HFB (935319815557) | No | 3 | 260 | 40 | |||
配送
| Part/12NC | 関税分類番号（米国)免責事項: | 輸出規制品目番号（米国） |
|---|---|---|
P1017NSN5HFB (935319815557) | 854231 | 3A991A2 |
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
P1017NSN5HFB (935319815557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
詳細 P1023
The P1023 and P1017 processors offer the value of integrated high-performance data path offload for networking protocols and dual e500 Power Architecture® cores for application software. The P1023 and P1017 are ideally suited for high-performance enterprise WLAN, fixed routers and security gateway applications. The P1023 device supports a 400–800 MHz performance range, along with advanced security and a rich set of interfaces—all delivered on 45 nm technology for low-power implementation.
The P1023 processor includes a performance-optimized implementation of the QorIQ® data path acceleration architecture (DPAA). This architecture provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. The DPAA significantly reduces software overhead associated with high touch packet forwarding operations. Examples of the types of packet processing services this architecture is optimized to support include traditional routing and bridging, firewall, VPN termination for IPsec and MACsec (a standardized form of Ethernet encapsulation that can be used to provide confidentiality).