Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特徴
QorIQ, 32-Bit Power Arch SoC, 4 X 1.5GHz, DDR3/3L, PCIe, SATA, SRIO, 1/10GbE, 0 to 105C, Rev 2
購入オプション
P3041NSN7PNC
生産終了 (EOL)
12NC: 935317936557
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Ethernet Type | 1GBaseT, XAUI |
Core: Number of cores (SPEC) | 4 |
PCIe | 4 |
GPIO | 32 |
Ethernet Type | 1GBaseT, XAUI |
Description | QorIQ, 32-Bit Power Arch SoC, 4 X 1.5GHz, DDR3/3L, PCIe, SATA, SRIO, 1/10GbE, 0 to 105C, Rev 2 |
Free Programmable CPU | e500mc |
Operating Frequency [Max] (MHz) | 1500 |
Frequency (Max) (kHz) | 1500000 |
L3 Cache (Max) (KB) | 1000 |
Ambient Operating Temperature (Min to Max) (℃) | 0 to 105 |
External Memory Supported | DDR3 SDRAM, DDR3L SDRAM |
Peripherals | DUART, ETH, ETH, I²C, PCIe, SPI, SRIO |
Memory Size (B) | 32000, 128000, 1000000 |
Peripheral Type | DUART, ETH, ETH, I²C, PCIe, SPI, SRIO |
PCIe | 4 x PCIe |
Ethernet w/ 1588 | 2 |
Serial Communication | 1 x SPI, 4 x I²C |
Cache (B) | 32000 |
Core Type | 4 x e500mc |
Number of pins | 1295 |
Package Style | BGA |
Peripheral Type | DUART, ETH, ETH, I²C, PCIe, SPI, SRIO |
Typical Power | 13.1 |
sRIO | 2 |
eTSEC | 15 |
Cache (KB) | 32 |
DUART | 2 |
TDM | 15 |
| パラメータ | 値 |
|---|---|
External Memory Interface [Number, Type] | 1000 x DDR3 SDRAM, 1000 x DDR3L SDRAM |
External Memory Interface | 1000 x DDR3 SDRAM, 1000 x DDR3L SDRAM |
I2C | 4 |
J1850 | 15 |
SLIC | 15 |
Security Status | COMPANY PUBLIC |
SPI | 1 |
Bus Frequency (typ) (MHz) | 667 |
L1 Cache (KB) | 32 |
Memory | SDRAM |
Core Type | Power Architecture has child e500, e500v2, e500mc |
Interfaces | Interfaces, Interfaces, Interfaces, Interfaces, Interfaces, Interfaces, Interfaces |
Internal Memory Supported | FLASH CACHE, L2 CACHE, L3 CACHE |
L2 Cache (Max) (KB) | 128 |
IBIZ LOADER | e500mc |
CLOUD_PROD3_NXP_CLOCK_SPEED_MAX | 1500 |
UART | 2 |
CLOUD_PROD2_NXP_CLOCK_SPEED_MAX | 1500 |
Communication protocol | DUART, ETH, I²C, PCIe, SPI, SRIO |
CLOUD PROD - Operating Frequency [Max] (MHz) | 1500 |
Core Type | e500mc |
Operating Temperature (Min-Max) (℃) | 0 to 105 |
Arm Core | e500mc |
Ethernet | 2 |
Ethernet | 1 x 1GBaseT, 1 x XAUI |
Master Interface | DUART, ETH, I²C, PCIe, SPI, SRIO |
Controller Interface | DUART, ETH, ETH, I²C, PCIe, SPI, SRIO |
Operating Frequency [Max] (MHz) | 1500 |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
|---|---|---|---|---|---|---|---|
P3041NSN7PNC(935317936557) | Yes | Yes Certificate Of Analysis (CoA) | Yes |  | e1 | REACH SVHC | 13973.9 |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
|---|---|---|---|---|---|---|---|
| 鉛フリーはんだ | 鉛フリーはんだ | 鉛フリーはんだ | |||||
P3041NSN7PNC (935317936557) | No | 3 | 245 | 30 | |||
配送
| Part/12NC | 関税分類番号（米国)免責事項: | 輸出規制品目番号（米国） | 足跡 | キャプチャ・シンボル |
|---|---|---|---|---|
P3041NSN7PNC (935317936557) | 854231 | 3A991A1 | PDF | Cadence Allegro(dra) | PDF | Orcad Capture 16.3(olb) |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
P3041NSN7PNC (935317936557) | NOTICE | 2021-09-09 | 2023-12-15 | - |
製品変更のお知らせ
| Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
|---|---|---|---|---|
P3041NSN7PNC (935317936557) | 2021-03-04 | 2021-03-05 | 202102034DN | Discontinuance of P1010P1020 P1022 P2020P3041 P4080 P5040 C290 MSC8156 BSC9131837x 8548 8572 8536 8544 Families |
P3041NSN7PNC (935317936557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
詳細 P3041
P3041 device is "Not recommended for new designs", please use the replacement families Power Architecture (T208x), Arm Architecture (LS1046, LS2080).
The QorIQ® P3041 processor is an optimized quad-core device that leverages architectural features pioneered in the P4 platform. Built on Power Architecture® technology, the P3041 fits into many of the same applications as the P4 platform processors, yet is designed to offer a more power- and cost-efficient solution.
The P3041 includes P4 platform features such as the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric which eliminates internal bottlenecks. This enables architectural compatibility from the P3041 to the P4 platform and also to the P5 platform, which uses the same architecture. P3041 is pin-compatible with P4040, P4080, P5010, and P5020.