Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
特徴
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
パッケージ
LFBGA96: plastic, low profile fine-pitch ball grid array package; 96 balls; 0.8 mm pitch; 13.5 mm x 5.5 mm x 1.5 mm body
購入オプション
SSTUA32866EC,518
製造中止
12NC: 935279441518
詳細
注文
SSTUA32866EC,551
製造中止
12NC: 935279441551
詳細
注文
SSTUA32866EC,557
製造中止
12NC: 935279441557
詳細
注文
SSTUA32866EC/G,518
製造中止
12NC: 935279442518
詳細
注文
SSTUA32866EC/G,551
製造中止
12NC: 935279442551
詳細
注文
SSTUA32866EC/G,557
製造中止
12NC: 935279442557
詳細
注文
操作機能
| パラメータ | 値 |
|---|---|
Number of pins | 96 |
Package Style | LFBGA |
Supply voltage (V) | 1.7 |
RF frequency [max] (MHz) | 0~450 |
Application | DDR2 400-667 Registered DIMMs |
Inputs | 14 (1:2) or 25 (1:1) x SSTL_18 |
Tamb [min] (°C) | 0~+70 |
Features | Parity checking |
| パラメータ | 値 |
|---|---|
Outputs | 25 (1:1) or 28 (1:2) x SSTL_18 |
Tamb (°C) | 0~+70 |
Security Status | COMPANY PUBLIC |
Description | 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications |
Operating Temperature (°C) | 0~+70 |
Operating Temperature (°C) | 0~+70 |
Operating frequency (MHz) | 0~450 |
tpd (ns) | 1.2~1.8 |
環境
| Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC |
|---|---|---|---|---|---|
SSTUA32866EC,518(935279441518) | No | No | - | REACH SVHC | |
SSTUA32866EC,551(935279441551) | No | No | - | REACH SVHC | |
SSTUA32866EC,557(935279441557) | No | No | - | REACH SVHC | |
SSTUA32866EC/G,518(935279442518) | Yes | Yes | No |  | REACH SVHC |
SSTUA32866EC/G,551(935279442551) | No | No | - | REACH SVHC | |
SSTUA32866EC/G,557(935279442557) | No | No | - | REACH SVHC |
品質
| Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
|---|---|---|---|---|---|
| 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||
SSTUA32866EC,518 (935279441518) | - | - | - | - | |
SSTUA32866EC,551 (935279441551) | - | - | - | - | |
SSTUA32866EC,557 (935279441557) | - | - | - | - | |
SSTUA32866EC/G,518 (935279442518) | - | 2 | 240 | 260 | |
SSTUA32866EC/G,551 (935279442551) | - | - | - | - | |
SSTUA32866EC/G,557 (935279442557) | - | - | - | - | |
配送
| Part/12NC | 関税分類番号（米国)免責事項: |
|---|---|
SSTUA32866EC,518 (935279441518) | 854239 |
SSTUA32866EC,551 (935279441551) | 854239 |
SSTUA32866EC,557 (935279441557) | 854239 |
SSTUA32866EC/G,518 (935279442518) | 854239 |
SSTUA32866EC/G,551 (935279442551) | 854239 |
SSTUA32866EC/G,557 (935279442557) | 854239 |
製造終了品・代替品データ
| Part/12NC | 製造終了のお知らせ | 最終購入日 | 最終納品日 | 交換 |
|---|---|---|---|---|
SSTUA32866EC/G,518 (935279442518) | - | 2005-06-30 | 2005-12-31 | SSTUB32866EC/G,518 (935281279518) |
詳細 SSTUA32866EC
Archived content is no longer updated and is made available for historical reference only.
The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
The SSTUA32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).