QorIQ® P1020 | NXP Semiconductors

オートモーティブ

インダストリアル

コンスーマ

テクノロジ

QorIQ® P1020 and P1011 Dual- and Single-Core Communications Processors

P1020 生産終了 (EOL)
  • このページでは、新規設計を推奨しない製品に関する情報を掲載しています。
NXP Priority Support: Helping You to Get to Market Faster

動画の上をクリックすると再生されます。

The QorIQ® P1 platform series, which includes the P1020 and P1011 communications processors, offers the value of extensive integration and high power for a wide variety of applications in the networking, telecom, aerospace, defense and industrial markets. The series provides dual-and single-core solutions for the 533 MHz to 800 MHz performance range, along with advanced security and a rich set of interfaces delivered on 45 nm technology for a low-power implementation.

The P1 platform series is perfectly suited for multiservice gateways, Ethernet switch controllers, wireless LAN access points and high-performance general-purpose control processor applications with tight thermal constraints.

The QorIQ P1 series consists of dual- and single-core products that are pin-compatible with QorIQ P2 platform products, offering a five-chip range of cost-effective solutions. Scaling from a single core at 533 MHz (P1011) to a dual core at 1.2 GHz per core (P2020), the two QorIQ platforms deliver an impressive 4.5X aggregate frequency range.

ブロック図

Freescale QorIQ P1020/11 Communication Processor Block Diagram

Freescale QorIQ P1020/11 Communication Processor Block Diagram
図を取得する PDF

Features

Core Complex

  • Dual (P1020) or single (P1011) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 800 MHz
  • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory

Networking Elements

  • Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSEC)
  • Two SGMII interfaces
  • Support for IEEE® 1588

Accelerators and Memory Control

  • DDR2/3 32-bit memory controller with ECC support
  • Integrated security engine
    • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
    • XOR acceleration

Basic Peripherals and Interconnect

  • Four-lane SERDES up to 3.125 GHz multiplexed across controllers
  • Two PCI Express® Gen1.0 interface controllers
  • Two USB2.0 controllers
  • Enhanced Local Bus Controller (eLBC)
  • TDM
  • eSDHC
  • Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

比較表

P1011 P1012 P1020 P1021
Cores 1 1 2 2
Core Frequency 533 - 800 MHz 533 - 800 MHz 533 - 800 MHz 533 - 800 MHz
L2 Cache 256KB 256KB 256KB 256KB
DDR 32-bit DDR2/DDR3 32-bit DDR2/DDR3 32-bit DDR2/DDR3 32-bit DDR2/DDR3
GbE 3 x 10/100/1000 3 x 10/100/1000 3 x 10/100/1000 3 x 10/100/1000
PCIe Gen 1.0 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES 2 controllers w/ 4 SERDES
USB 2.0 2 1 2 2
Memory Card SD/MMC SD/MMC SD/MMC SD/MMC
Other interfaces SPI, 2xI²C, DUART SPI, 2xI²C, DUART SPI, 2xI²C, DUART SPI, 2xI²C, DUART
TDM or QUICC Engine TDM QUICC Engine TDM QUICC Engine
Accelerators SEC3.3 SEC3.3 SEC3.3 SEC3.3

購入/パラメータ

1-10 の 22 結果

除外 22 NRND

パーツ

説明を表示

コンピュータ支援設計 モデル

状況

パッケージタイプ

パッケージ端子数

コア・タイプ

コア：コア数 - 仕様

動作周波数[最大](MHz)

PCIe

対応する外部メモリ

Ambient Operating Temperature (Min to Max) (℃)

P1011NSE2DFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

533

2

DDR2 SDRAM, DDR3 SDRAM

0 to 125

P1011NSE2FFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

667

2

DDR2 SDRAM, DDR3 SDRAM

0 to 125

P1011NSE2HFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

800

2

DDR2 SDRAM, DDR3 SDRAM

0 to 125

P1011NSN2DFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

533

2

DDR2 SDRAM, DDR3 SDRAM

0 to 125

P1011NSN2FFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

667

2

DDR2 SDRAM, DDR3 SDRAM

0 to 125

P1011NSN2HFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

800

2

DDR2 SDRAM, DDR3 SDRAM

-40 to 125

P1011NXE2DFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

533

2

DDR2 SDRAM, DDR3 SDRAM

-40 to 125

P1011NXE2FFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

667

2

DDR2 SDRAM, DDR3 SDRAM

-40 to 125

P1011NXE2HFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

800

2

DDR2 SDRAM, DDR3 SDRAM

-40 to 125

P1011NXN2DFB
データ・シート

生産終了 (EOL)

HBGA689

689

e500

1

533

2

DDR2 SDRAM, DDR3 SDRAM

-40 to 125

N true 0 PSPP1020ja 43 アプリケーション・ノート Application Note t789 28 アプリケーション・ノート・ソフトウェア Application Note Software t783 1 エンジニアリング・ブリテン Technical Notes t521 2 サポート情報 Supporting Information t531 2 データ・シート Data Sheet t520 2 ファクト・シート Fact Sheet t523 2 ホワイト・ペーパ White Paper t530 1 リファレンス・マニュアル Reference Manual t877 4 製品概要 Product Brief t532 1 ja 2 1 6 English QorIQ<sup>&#174;</sup> communications platforms are the next-generation evolution of our leading PowerQUICC<sup>&#174;</sup> communications processors. Built using high-performance Power Architecture&#174; cores, QorIQ platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. 1213558819933721477267 PSP 384.7 KB None None documents None 1213558819933721477267 /docs/en/fact-sheet/QorIQ_P1.pdf 384740 /docs/en/fact-sheet/QorIQ_P1.pdf QORIQ_P1 N 2016-10-31 QorIQ P1020/P1011 Communications Processors - Fact Sheet /docs/en/fact-sheet/QorIQ_P1.pdf /docs/en/fact-sheet/QorIQ_P1.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf en Nov 19, 2013 Fact Sheet t523 ファクト・シート Fact Sheet N QorIQ P1020/P1011 Communications Processors - Fact Sheet 2 0 English This document provides an overview of features and functionality of the QorIQ<sup>&#174;</sup>&#8482; P1020 integrated processor. The P1020 combines dual Power Architecture&#8482; e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications. 1226946693082725963484 PSP 544.3 KB None None documents None 1226946693082725963484 /docs/en/product-brief/P1020PB.pdf 544292 /docs/en/product-brief/P1020PB.pdf P1020PB N 2008-11-17 P1020 Product Brief /docs/en/product-brief/P1020PB.pdf /docs/en/product-brief/P1020PB.pdf Product Brief N Y 899114358132306053 2022-12-07 pdf en Nov 17, 2008 Product Brief t532 製品概要 Product Brief Y N P1020 Product Brief false ja ja データ・シート Data Sheet 2 3 1 English This document describes the electrical characteristics of P1020 QorIQ<sup>&#174;</sup> Integrated Processor. 1312992986586725668561 PSP 2.3 MB Registration without Disclaimer None documents Extended 1312992986586725668561 /secured/assets/documents/en/data-sheet/P1020EC.pdf 2336975 /secured/assets/documents/en/data-sheet/P1020EC.pdf P1020EC documents Y N 2016-10-31 P1020 QorIQ Integrated Processor Hardware Specifications /webapp/Download?colCode=P1020EC&lang_cd=ja /secured/assets/documents/en/data-sheet/P1020EC.pdf Data Sheet N 980000996212993340 2022-12-07 pdf Y en Mar 18, 2012 980000996212993340 Data Sheet N P1020 QorIQ Integrated Processor Hardware Specifications 4 1 English This document describes the P1011 electrical characteristics. 1312992216714716096422 PSP 2.3 MB Registration without Disclaimer None documents Extended 1312992216714716096422 /secured/assets/documents/en/data-sheet/P1011EC.pdf 2332581 /secured/assets/documents/en/data-sheet/P1011EC.pdf P1011EC documents Y N 2016-10-31 P1011 QorIQ Integrated Processor Hardware Specifications /webapp/Download?colCode=P1011EC&lang_cd=ja /secured/assets/documents/en/data-sheet/P1011EC.pdf Data Sheet N 980000996212993340 2022-12-07 pdf Y en Mar 18, 2012 980000996212993340 Data Sheet N P1011 QorIQ Integrated Processor Hardware Specifications リファレンス・マニュアル Reference Manual 4 5 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM&lang_cd=ja /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 6 6 English This reference manual defines the functionality of the P1020. This device integrates dual e500v2 processor cores based on Power Architecture&#8482; technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500v2 core is a low-power implementation of resources defined for embedded processors by the Power instruction set architecture (Power ISA). The e500 is a 32-bit implementation using the lower words in the 64-bit general-purpose registers (GPR 1262304915865706945844 PSP 21.0 MB Registration without Disclaimer None documents Extended 1262304915865706945844 /secured/assets/documents/en/reference-manual/P1020RM.pdf 20994415 /secured/assets/documents/en/reference-manual/P1020RM.pdf P1020RM documents Y N 2016-10-31 P1020 QorIQ Integrated Processor Reference Manual /webapp/Download?colCode=P1020RM&lang_cd=ja /secured/assets/documents/en/reference-manual/P1020RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jan 28, 2013 500633505221135046 Reference Manual N P1020 QorIQ Integrated Processor Reference Manual 7 0 English Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala 1247173677125723218813 PSP 1.5 MB Registration without Disclaimer None documents Extended 1247173677125723218813 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 1486324 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf EMBMCRM documents Y N 2016-10-31 Embedded Multicore: An Introduction /webapp/Download?colCode=EMBMCRM&lang_cd=ja /secured/assets/documents/en/reference-manual/EMBMCRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 20, 2009 500633505221135046 Reference Manual Y N Embedded Multicore: An Introduction 8 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual アプリケーション・ノート Application Note 28 9 0 English Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. 1500876825316705874194 PSP 349.9 KB None None documents None 1500876825316705874194 /docs/en/application-note/AN5079.pdf 349919 /docs/en/application-note/AN5079.pdf AN5079 documents N N 2017-07-23 AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf /docs/en/application-note/AN5079.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 10 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 11 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 12 1 English AN4259: This document provides recommendations for new designs based on the P1020 QorIQ<sup>&#174;</sup> integrated processors family that includes P1011, P1012, P1015, P1016, P1021, P1024, and P1025. P1020 combines single or dual e500v2 processor cores built on Power Architecture&#174; technology with system logic required for networking, wireless infrastructure, and telecommunications applications. 1312958093532718295022 PSP 485.3 KB Registration without Disclaimer None documents Extended 1312958093532718295022 /secured/assets/documents/en/application-note/AN4259.pdf 485314 /secured/assets/documents/en/application-note/AN4259.pdf AN4259 documents Y N 2016-10-31 AN4259, P1020 Family of QorIQ Integrated Processors Design Checklist - Application Note /webapp/Download?colCode=AN4259&lang_cd=ja /secured/assets/documents/en/application-note/AN4259.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 2, 2014 645036621402383989 Application Note N AN4259, P1020 Family of QorIQ Integrated Processors Design Checklist - Application Note 13 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=ja /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 14 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 15 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 16 1 English This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. 1329517560294722281831 PSP 216.6 KB None None documents None 1329517560294722281831 /docs/en/application-note/AN4375.pdf 216552 /docs/en/application-note/AN4375.pdf AN4375 documents N N 2016-10-31 QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf /docs/en/application-note/AN4375.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 21, 2012 645036621402383989 Application Note N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 17 2 English This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. 1229718093838710459075 PSP 334.2 KB None None documents None 1229718093838710459075 /docs/en/application-note/AN3659.pdf 334243 /docs/en/application-note/AN3659.pdf AN3659 documents N N 2016-10-31 Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf /docs/en/application-note/AN3659.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 15, 2012 645036621402383989 Application Note N Booting from On-Chip ROM (eSDHC or eSPI) 18 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 19 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 20 0 English 1287581868481730872047 PSP 142.0 KB None None documents None 1287581868481730872047 /docs/en/application-note/AN3423.pdf 141965 /docs/en/application-note/AN3423.pdf AN3423 documents N 2016-10-31 Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf /docs/en/application-note/AN3423.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 6, 2010 645036621402383989 Application Note N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 21 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 22 1 English This application note describes the recommended microcode download procedure on QUICC Engine<sup>&#174;</sup> block-enabled devices, and when and how microcode should be downloaded. 1254777635514719266846 PSP 187.2 KB Registration without Disclaimer None documents Extended 1254777635514719266846 /secured/assets/documents/en/application-note/AN3946.pdf 187225 /secured/assets/documents/en/application-note/AN3946.pdf AN3946 documents Y N 2016-10-31 Downloading Microcode On QUICC Engine™ Block-Enabled Devices /webapp/Download?colCode=AN3946&lang_cd=ja /secured/assets/documents/en/application-note/AN3946.pdf Application Note N 645036621402383989 2024-11-26 pdf Y en Apr 1, 2010 645036621402383989 Application Note Y N Downloading Microcode On QUICC Engine™ Block-Enabled Devices 23 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 24 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 25 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 26 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646&lang_cd=ja /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 27 1 English Application Note 1060017730134725666689 PSP 612.9 KB None None documents None 1060017730134725666689 /docs/en/application-note/AN2490.pdf 612895 /docs/en/application-note/AN2490.pdf AN2490 documents N 2016-10-31 MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf /docs/en/application-note/AN2490.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 23, 2009 645036621402383989 Application Note N MPC603e and e500 Register Model Comparison 28 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869&lang_cd=ja /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 29 0 English AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. 1202329207598722883383 PSP 519.9 KB None None documents None 1202329207598722883383 /docs/en/application-note/AN3542.pdf 519909 /docs/en/application-note/AN3542.pdf AN3542 documents N 2016-10-31 AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf /docs/en/application-note/AN3542.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jan 25, 2008 645036621402383989 Application Note N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 30 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 31 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 32 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 33 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 34 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 35 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 36 0 English AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations. 1112972998032717039588 PSP 799.6 KB None None documents None 1112972998032717039588 /docs/en/application-note/AN2665.pdf 799625 /docs/en/application-note/AN2665.pdf AN2665 documents N 2016-10-31 AN2665, e500 Software Optimization Guide (eSOG) - Application Notes /docs/en/application-note/AN2665.pdf /docs/en/application-note/AN2665.pdf Application Note N 645036621402383989 2022-12-07 pdf en Apr 8, 2005 645036621402383989 Application Note N AN2665, e500 Software Optimization Guide (eSOG) - Application Notes アプリケーション・ノート・ソフトウェア Application Note Software 1 37 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies エンジニアリング・ブリテン Technical Notes 2 38 0 English This document describes the functionality of NXP&#8217;s integrated security engine (SEC 3.3.2). The SEC 3.3.2 is designed to off-load computationally intensive security functions, such as key generation and exchange, authentication, and bulk encryption from the processor core of the SoC. It is optimized to process all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, 802.11i, and WiMAX, 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS. The SEC 3.3.2 is derived from integrated sec 1308819453950712916284 PSP 1.7 MB Registration without Disclaimer None documents Extended 1308819453950712916284 /secured/assets/documents/en/engineering-bulletin/EB748.pdf 1729498 /secured/assets/documents/en/engineering-bulletin/EB748.pdf EB748 documents Y N 2016-10-31 Security Engine (SEC) 3.3.2 Engineering Bulletin /webapp/Download?colCode=EB748&lang_cd=ja /secured/assets/documents/en/engineering-bulletin/EB748.pdf Technical Notes N 389245547230346745 2022-12-07 pdf Y en Jun 22, 2011 389245547230346745 Technical Notes N Security Engine (SEC) 3.3.2 Engineering Bulletin 39 0 English Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices 1299186935006725024525 PSP 492.6 KB Registration without Disclaimer None documents Extended 1299186935006725024525 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 492591 /secured/assets/documents/en/engineering-bulletin/EB739.pdf EB739 documents Y N 2016-10-31 COM Express Pin Assignments for QorIQ Devices /webapp/Download?colCode=EB739&lang_cd=ja /secured/assets/documents/en/engineering-bulletin/EB739.pdf Technical Notes N 389245547230346745 2022-12-07 pdf Y en Mar 3, 2011 389245547230346745 Technical Notes N COM Express Pin Assignments for QorIQ Devices ファクト・シート Fact Sheet 1 40 1 English P1020/P1011 Reference Board Fact Sheet 1267217109362677829289 PSP 369.1 KB None None documents None 1267217109362677829289 /docs/en/fact-sheet/P1020RDBFS.pdf 369086 /docs/en/fact-sheet/P1020RDBFS.pdf P1020RDBFS documents N N 2016-10-31 P1020RDB Fact Sheet /docs/en/fact-sheet/P1020RDBFS.pdf /docs/en/fact-sheet/P1020RDBFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Dec 14, 2010 736675474163315314 Fact Sheet N P1020RDB Fact Sheet サポート情報 Supporting Information 2 41 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 42 2 English 1264169315462703319768 PSP 246.8 KB None None documents None 1264169315462703319768 /docs/en/supporting-information/P102xFAMPECI.pdf 246832 /docs/en/supporting-information/P102xFAMPECI.pdf P102XFAMPECI documents N N 2016-10-31 P1020 and P1021 Family Customer Export Control Information /docs/en/supporting-information/P102xFAMPECI.pdf /docs/en/supporting-information/P102xFAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N P1020 and P1021 Family Customer Export Control Information ホワイト・ペーパ White Paper 1 43 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper false 0 P1020 downloads ja true 1 Y PSP アプリケーション・ノート 28 /docs/en/application-note/AN5079.pdf 2017-07-23 1500876825316705874194 PSP 9 Jul 24, 2017 Application Note Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. None /docs/en/application-note/AN5079.pdf English documents 349919 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5079.pdf AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 349.9 KB AN5079 N 1500876825316705874194 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 10 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 11 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /secured/assets/documents/en/application-note/AN4259.pdf 2016-10-31 1312958093532718295022 PSP 12 Jun 2, 2014 Application Note AN4259: This document provides recommendations for new designs based on the P1020 QorIQ<sup>&#174;</sup> integrated processors family that includes P1011, P1012, P1015, P1016, P1021, P1024, and P1025. P1020 combines single or dual e500v2 processor cores built on Power Architecture&#174; technology with system logic required for networking, wireless infrastructure, and telecommunications applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4259.pdf English documents 485314 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN4259&lang_cd=ja AN4259, P1020 Family of QorIQ Integrated Processors Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4259.pdf documents 645036621402383989 Application Note N en Extended pdf 1 Y N AN4259, P1020 Family of QorIQ Integrated Processors Design Checklist - Application Note 485.3 KB AN4259 N 1312958093532718295022 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 13 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=ja AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 14 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 15 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4375.pdf 2016-10-31 1329517560294722281831 PSP 16 Jun 21, 2012 Application Note This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. None /docs/en/application-note/AN4375.pdf English documents 216552 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4375.pdf QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf documents 645036621402383989 Application Note N en None pdf 1 N N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 216.6 KB AN4375 N 1329517560294722281831 /docs/en/application-note/AN3659.pdf 2016-10-31 1229718093838710459075 PSP 17 Jun 15, 2012 Application Note This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. None /docs/en/application-note/AN3659.pdf English documents 334243 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3659.pdf Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf documents 645036621402383989 Application Note N en None pdf 2 N N Booting from On-Chip ROM (eSDHC or eSPI) 334.2 KB AN3659 N 1229718093838710459075 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 18 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 19 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3423.pdf 2016-10-31 1287581868481730872047 PSP 20 Oct 6, 2010 Application Note None /docs/en/application-note/AN3423.pdf English documents 141965 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3423.pdf Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf documents 645036621402383989 Application Note N en None pdf 0 N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 142.0 KB AN3423 N 1287581868481730872047 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 21 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /secured/assets/documents/en/application-note/AN3946.pdf 2016-10-31 1254777635514719266846 PSP 22 Apr 1, 2010 Application Note This application note describes the recommended microcode download procedure on QUICC Engine<sup>&#174;</sup> block-enabled devices, and when and how microcode should be downloaded. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3946.pdf English documents 187225 None 645036621402383989 2024-11-26 Y /webapp/Download?colCode=AN3946&lang_cd=ja Downloading Microcode On QUICC Engine™ Block-Enabled Devices /secured/assets/documents/en/application-note/AN3946.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N Downloading Microcode On QUICC Engine™ Block-Enabled Devices 187.2 KB AN3946 N 1254777635514719266846 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 23 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 24 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 25 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 26 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646&lang_cd=ja Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /docs/en/application-note/AN2490.pdf 2016-10-31 1060017730134725666689 PSP 27 Sep 23, 2009 Application Note Application Note None /docs/en/application-note/AN2490.pdf English documents 612895 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2490.pdf MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf documents 645036621402383989 Application Note N en None pdf 1 N MPC603e and e500 Register Model Comparison 612.9 KB AN2490 N 1060017730134725666689 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 28 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869&lang_cd=ja Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3542.pdf 2016-10-31 1202329207598722883383 PSP 29 Jan 25, 2008 Application Note AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. None /docs/en/application-note/AN3542.pdf English documents 519909 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3542.pdf AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 519.9 KB AN3542 N 1202329207598722883383 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 30 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 31 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 32 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 33 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 34 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 35 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 /docs/en/application-note/AN2665.pdf 2016-10-31 1112972998032717039588 PSP 36 Apr 8, 2005 Application Note AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations. None /docs/en/application-note/AN2665.pdf English documents 799625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2665.pdf AN2665, e500 Software Optimization Guide (eSOG) - Application Notes /docs/en/application-note/AN2665.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN2665, e500 Software Optimization Guide (eSOG) - Application Notes 799.6 KB AN2665 N 1112972998032717039588 アプリケーション・ノート・ソフトウェア 1 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 37 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 エンジニアリング・ブリテン 2 /secured/assets/documents/en/engineering-bulletin/EB748.pdf 2016-10-31 1308819453950712916284 PSP 38 Jun 22, 2011 Technical Notes This document describes the functionality of NXP&#8217;s integrated security engine (SEC 3.3.2). The SEC 3.3.2 is designed to off-load computationally intensive security functions, such as key generation and exchange, authentication, and bulk encryption from the processor core of the SoC. It is optimized to process all cryptographic algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, 802.11i, and WiMAX, 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS. The SEC 3.3.2 is derived from integrated sec Registration without Disclaimer /secured/assets/documents/en/engineering-bulletin/EB748.pdf English documents 1729498 None 389245547230346745 2022-12-07 Y /webapp/Download?colCode=EB748&lang_cd=ja Security Engine (SEC) 3.3.2 Engineering Bulletin /secured/assets/documents/en/engineering-bulletin/EB748.pdf documents 389245547230346745 Technical Notes N en Extended pdf 0 Y N Security Engine (SEC) 3.3.2 Engineering Bulletin 1.7 MB EB748 N 1308819453950712916284 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 2016-10-31 1299186935006725024525 PSP 39 Mar 3, 2011 Technical Notes Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices Registration without Disclaimer /secured/assets/documents/en/engineering-bulletin/EB739.pdf English documents 492591 None 389245547230346745 2022-12-07 Y /webapp/Download?colCode=EB739&lang_cd=ja COM Express Pin Assignments for QorIQ Devices /secured/assets/documents/en/engineering-bulletin/EB739.pdf documents 389245547230346745 Technical Notes N en Extended pdf 0 Y N COM Express Pin Assignments for QorIQ Devices 492.6 KB EB739 N 1299186935006725024525 サポート情報 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 41 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/P102xFAMPECI.pdf 2016-10-31 1264169315462703319768 PSP 42 Dec 10, 2010 Supporting Information None /docs/en/supporting-information/P102xFAMPECI.pdf English documents 246832 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/P102xFAMPECI.pdf P1020 and P1021 Family Customer Export Control Information /docs/en/supporting-information/P102xFAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 2 N N P1020 and P1021 Family Customer Export Control Information 246.8 KB P102XFAMPECI N 1264169315462703319768 データ・シート 2 /secured/assets/documents/en/data-sheet/P1020EC.pdf 2016-10-31 1312992986586725668561 PSP 3 Mar 18, 2012 Data Sheet This document describes the electrical characteristics of P1020 QorIQ<sup>&#174;</sup> Integrated Processor. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P1020EC.pdf English documents 2336975 None 980000996212993340 2022-12-07 Y /webapp/Download?colCode=P1020EC&lang_cd=ja P1020 QorIQ Integrated Processor Hardware Specifications /secured/assets/documents/en/data-sheet/P1020EC.pdf documents 980000996212993340 Data Sheet N en Extended pdf 1 Y N P1020 QorIQ Integrated Processor Hardware Specifications 2.3 MB P1020EC N 1312992986586725668561 /secured/assets/documents/en/data-sheet/P1011EC.pdf 2016-10-31 1312992216714716096422 PSP 4 Mar 18, 2012 Data Sheet This document describes the P1011 electrical characteristics. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P1011EC.pdf English documents 2332581 None 980000996212993340 2022-12-07 Y /webapp/Download?colCode=P1011EC&lang_cd=ja P1011 QorIQ Integrated Processor Hardware Specifications /secured/assets/documents/en/data-sheet/P1011EC.pdf documents 980000996212993340 Data Sheet N en Extended pdf 1 Y N P1011 QorIQ Integrated Processor Hardware Specifications 2.3 MB P1011EC N 1312992216714716096422 ファクト・シート 2 /docs/en/fact-sheet/P1020RDBFS.pdf 2016-10-31 1267217109362677829289 PSP 40 Dec 14, 2010 Fact Sheet P1020/P1011 Reference Board Fact Sheet None /docs/en/fact-sheet/P1020RDBFS.pdf English documents 369086 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/P1020RDBFS.pdf P1020RDB Fact Sheet /docs/en/fact-sheet/P1020RDBFS.pdf documents 736675474163315314 Fact Sheet N en None pdf 1 N N P1020RDB Fact Sheet 369.1 KB P1020RDBFS N 1267217109362677829289 /docs/en/fact-sheet/QorIQ_P1.pdf 2016-10-31 1213558819933721477267 PSP 1 Nov 19, 2013 Fact Sheet ファクト・シート QorIQ<sup>&#174;</sup> communications platforms are the next-generation evolution of our leading PowerQUICC<sup>&#174;</sup> communications processors. Built using high-performance Power Architecture&#174; cores, QorIQ platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. None /docs/en/fact-sheet/QorIQ_P1.pdf English 384740 None Fact Sheet 2022-12-07 /docs/en/fact-sheet/QorIQ_P1.pdf QorIQ P1020/P1011 Communications Processors - Fact Sheet /docs/en/fact-sheet/QorIQ_P1.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 6 N QorIQ P1020/P1011 Communications Processors - Fact Sheet 384.7 KB QORIQ_P1 N 1213558819933721477267 ホワイト・ペーパ 1 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 43 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 リファレンス・マニュアル 4 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 5 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM&lang_cd=ja EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /secured/assets/documents/en/reference-manual/P1020RM.pdf 2016-10-31 1262304915865706945844 PSP 6 Jan 28, 2013 Reference Manual This reference manual defines the functionality of the P1020. This device integrates dual e500v2 processor cores based on Power Architecture&#8482; technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The e500v2 core is a low-power implementation of resources defined for embedded processors by the Power instruction set architecture (Power ISA). The e500 is a 32-bit implementation using the lower words in the 64-bit general-purpose registers (GPR Registration without Disclaimer /secured/assets/documents/en/reference-manual/P1020RM.pdf English documents 20994415 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=P1020RM&lang_cd=ja P1020 QorIQ Integrated Processor Reference Manual /secured/assets/documents/en/reference-manual/P1020RM.pdf documents 500633505221135046 Reference Manual N en Extended pdf 6 Y N P1020 QorIQ Integrated Processor Reference Manual 21.0 MB P1020RM N 1262304915865706945844 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 2016-10-31 1247173677125723218813 PSP 7 Jul 20, 2009 Reference Manual Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala Registration without Disclaimer /secured/assets/documents/en/reference-manual/EMBMCRM.pdf English documents 1486324 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EMBMCRM&lang_cd=ja Embedded Multicore: An Introduction /secured/assets/documents/en/reference-manual/EMBMCRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N Embedded Multicore: An Introduction 1.5 MB EMBMCRM N 1247173677125723218813 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 8 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB 製品概要 1 /docs/en/product-brief/P1020PB.pdf 2008-11-17 1226946693082725963484 PSP 2 Nov 17, 2008 Product Brief 製品概要 This document provides an overview of features and functionality of the QorIQ<sup>&#174;</sup>&#8482; P1020 integrated processor. The P1020 combines dual Power Architecture&#8482; e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications. None /docs/en/product-brief/P1020PB.pdf English 544292 None Product Brief 2022-12-07 /docs/en/product-brief/P1020PB.pdf P1020 Product Brief /docs/en/product-brief/P1020PB.pdf documents 899114358132306053 Product Brief N Y en None Y t532 pdf 0 N P1020 Product Brief 544.3 KB P1020PB N 1226946693082725963484 true Y Products

ドキュメント

クイック・リファレンス ドキュメンテーションの種類.

フィルタ

43 / 43 ドキュメント

コンパクトリスト

アプリケーション・ノート (28)
アプリケーション・ノート・ソフトウェア (1)
エンジニアリング・ブリテン (2)
サポート情報 (2)
データ・シート (2)
ファクト・シート (2)
ホワイト・ペーパ (1)
リファレンス・マニュアル (4)
製品概要 (1)

デザイン・ファイル

ソフトウェア

クイック・リファレンス ソフトウェア・タイプ.

フィルタ

3 ソフトウェア・ファイル

注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。

トレーニング

フィルタ

1 トレーニング

サポート

お困りのことは何ですか？?

検索