QorIQ® T1024 | NXP Semiconductors

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QorIQ® T1024/14 and T1023/13 Dual- and Single-Core Communications Processors

T1024 アクティブ
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The QorIQ® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications and industrial networked applications. The QorIQ T Series platform offers optimized features for the industrial market, including a display interface unit for HMI, the QUICC Engine® for industrial protocol offload and ECC support for high reliability “always on” applications.

The T1024 and T1014 processors come in a full-featured 23x23 mm package, which provides scalable, pin compatibility with the quad-core T1042 processor, and even the eight core T2081 processor for price and power scaling with a single system design.

The QorIQ T1023 and T1013 communications processors are interface and power-optimized SoCs designed to deliver impressive single- or dual-core performance for cost and power sensitive networking and industrial systems. Both versions offer an excellent software compatible 64-bit and I/O upgrade path for the popular QorIQ P10XX family of 32-bit communications processors.

ブロック図

図を選択する。:

31538 T1023 BD

QorIQ T1013 and T1023 Communications Processors

31538 T1024 BD

QorIQ T1014 and T1024 Communications Processors
図を取得する PDF

Features

Core Complex

  • Single and dual e5500 cores, built on Power Architecture technology
  • Up to 1.4 GHz with 64-bit ISA support
  • Three levels of instructions: user, supervisor, hypervisor
  • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
  • 256 KB backside L2 cache

Networking Elements

  • SerDes
    • Four lanes at up to 10 Gbps
    • Supports SGMII, QSGMII, PCIe and SATA
  • Ethernet Interfaces
    • 1x 10GbE and 3x 1GbE or 4x 1Gbe Gigabit Ethernet interfaces, with MACsec on all ports

Accelerators and Memory Control

  • 32/64-bit DDR3L/4 SDRAM memory controller with ECC support
    • Up to 1600 MT/s
  • DPAA incorporating acceleration for the following functions: packet parsing, classification and distribution
    • Queue management for scheduling, packet sequencing and congestion management
    • Hardware buffer management for buffer allocation and de-allocation
    • Integrated security acceleration (SEC)

Basic Peripherals and Interconnect

  • CoreNet® platform cache
    • 256 KB shared platform cache
  • Hierarchical interconnect fabric
    • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
  • Additional peripheral interfaces one Serial ATA (SATA 2.0) controllers
    • Two high-speed USB 2.0 controllers with integrated PHYs
    • Enhanced secure digital host controller (SD/MMC/eMMC)
    • Enhanced serial peripheral interface (eSPI)
    • Two I²C controllers
    • Four UARTS
    • Integrated flash controller supporting NAND and NOR flash
  • DMA
    • Dual four channel
    • Up to 4.1 Gbps Ethernet MACs as part of DPAA
  • QUICC Engine®
    • Support for legacy protocols TDM, HDLC, UART and ISDN
  • High-speed peripheral interfaces
    • Three PCI Express® 2.0 controllers

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
  • QorIQ® trust architecture
    • Secure boot, secure debug, tamper detection, volatile key storage
  • This product is included in Our product longevity program, with assured supply for a minimum of 10 years after launch

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Product Detail
F104S8AF104X8A
DescriptionQSGMII PHY Standard TemperatureQSGMII PHY Extended Temperature
Operating Temperature (°C)0 - 125-40 - 125
Package Type12x12, QFN, 138-pin, 0.65mm pin pitch12x12, QFN, 138-pin, 0.65mm pin pitch
Read More

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N true 0 PSPT1024ja 25 アプリケーション・ノート Application Note t789 12 サポート情報 Supporting Information t531 3 データ・シート Data Sheet t520 2 ファクト・シート Fact Sheet t523 1 ホワイト・ペーパ White Paper t530 1 リファレンス・マニュアル Reference Manual t877 5 製品概要 Product Brief t532 1 ja 1 1 1 Chinese 1396026129133725006112zh PSP 139.0 KB None None documents None 1396026129133725006112 /docs/zh/fact-sheet/T1024FS.pdf 139002 /docs/zh/fact-sheet/T1024FS.pdf T1024FS documents N N 2014-04-08 QorIQ<sup>&#174;</sup> T1024/14 and T1023/13 Communications Processors - Fact Sheet /docs/zh/fact-sheet/T1024FS.pdf /docs/zh/fact-sheet/T1024FS.pdf /docs/zh/fact-sheet/T1024FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 N zh 736675474163315314 Fact Sheet N QorIQ T1024/14和T1023/13通信处理器 - 简介 2 English QorIQ<sup>&#174;</sup>, T Series, T1 family, T1, T1023, T1013, T1024, T1014 1396026129133725006112 PSP 139.0 KB None None documents None 1396026129133725006112 /docs/en/fact-sheet/T1024FS.pdf 139002 /docs/en/fact-sheet/T1024FS.pdf T1024FS N N 2014-04-08 QorIQ<sup>&#174;</sup> T1024/14 and T1023/13 Communications Processors - Fact Sheet /docs/en/fact-sheet/T1024FS.pdf /docs/en/fact-sheet/T1024FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Nov 4, 2015 Fact Sheet t523 ファクト・シート Fact Sheet Y N QorIQ<sup>&#174;</sup> T1024/14 and T1023/13 Communications Processors - Fact Sheet false ja ja データ・シート Data Sheet 2 2 1 English T1024 QorIQ advanced multicore processor combines two 64-bit ISA Power Architecture processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1437668827017691600221 PSP 3.3 MB Registration without Disclaimer documents Extended 1437668827017691600221 /secured/assets/documents/en/data-sheet/T1024.pdf 3308150 /secured/assets/documents/en/data-sheet/T1024.pdf T1024 documents Y N 2015-07-23 QorIQ T1024, T1014 Data Sheet /webapp/Download?colCode=T1024&lang_cd=ja /secured/assets/documents/en/data-sheet/T1024.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Dec 21, 2016 980000996212993340 Data Sheet N QorIQ T1024, T1014 Data Sheet 3 1 English T1023 QorIQ advanced multicore processor combines two 64-bit ISA Power Architecture processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1437669029273714054537 PSP 2.9 MB Registration without Disclaimer documents Extended 1437669029273714054537 /secured/assets/documents/en/data-sheet/T1023.pdf 2947193 /secured/assets/documents/en/data-sheet/T1023.pdf T1023 documents Y N 2015-07-23 QorIQ T1023, T1013 Data Sheet /webapp/Download?colCode=T1023&lang_cd=ja /secured/assets/documents/en/data-sheet/T1023.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Dec 21, 2016 980000996212993340 Data Sheet N QorIQ T1023, T1013 Data Sheet リファレンス・マニュアル Reference Manual 5 4 1 English The QorIQ<sup>&#174;</sup> T1024/23 family of communications processors combines single or dual 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network interfaces required for networking and telecommunications. 1433722816645718734966 PSP 21.4 MB Registration without Disclaimer None documents Extended 1433722816645718734966 /secured/assets/documents/en/reference-manual/T1024RM.pdf 21449134 /secured/assets/documents/en/reference-manual/T1024RM.pdf T1024RM documents Y N 2018-09-04 QorIQ T1024 Reference Manual /webapp/Download?colCode=T1024RM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1024RM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Sep 5, 2018 500633505221135046 Reference Manual Y N QorIQ T1024 Reference Manual 5 9 English This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. 1233608188787709580857 PSP 13.4 MB Registration without Disclaimer None documents Extended 1233608188787709580857 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 13369144 /secured/assets/documents/en/reference-manual/QEIWRM.pdf QEIWRM documents Y N 2016-10-31 QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /webapp/Download?colCode=QEIWRM&lang_cd=ja /secured/assets/documents/en/reference-manual/QEIWRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en May 3, 2018 500633505221135046 Reference Manual Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 6 4 English e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. 1320675592951722488289 PSP 3.7 MB Registration without Disclaimer None documents Extended 1320675592951722488289 /secured/assets/documents/en/reference-manual/e5500RM.pdf 3661467 /secured/assets/documents/en/reference-manual/e5500RM.pdf E5500RM documents Y N 2011-11-07 e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /webapp/Download?colCode=E5500RM&lang_cd=ja /secured/assets/documents/en/reference-manual/e5500RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 28, 2015 500633505221135046 Reference Manual Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 7 0 English T1024DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. 1437759164492730652137 PSP 16.2 MB Registration without Disclaimer None documents Extended 1437759164492730652137 /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf 16199184 /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf T1024DPAARM documents Y N 2016-10-31 T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual /webapp/Download?colCode=T1024DPAARM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 24, 2015 500633505221135046 Reference Manual Y N T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual 8 0 English T1024SECRM: This manual documents the T1024's security engine, the cryptographic acceleration and offloading hardware. 1437768398339710109264 PSP 8.0 MB Registration without Disclaimer None documents Extended 1437768398339710109264 /secured/assets/documents/en/reference-manual/T1024SECRM.pdf 8037292 /secured/assets/documents/en/reference-manual/T1024SECRM.pdf T1024SECRM documents Y N 2015-07-24 T1024SECRM, QorIQ<sup>&#174;</sup> T1024 Security (SEC) Reference Manual - Reference Manual /webapp/Download?colCode=T1024SECRM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1024SECRM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jul 24, 2015 500633505221135046 Reference Manual Y N T1024SECRM, QorIQ<sup>&#174;</sup> T1024 Security (SEC) Reference Manual - Reference Manual アプリケーション・ノート Application Note 12 9 0 English This application note introduces the LS1xxxx and LS2xxxx devices Thermal Management Unit (TMU). TMU Thermal Measurement Temperature Sensor Heat power 1651046281017726871122 PSP 241.6 KB None None documents None 1651046281017726871122 /docs/en/application-note/AN12310.pdf 241590 /docs/en/application-note/AN12310.pdf AN12310 documents N N 2022-04-27 Thermal Management Unit Usage /docs/en/application-note/AN12310.pdf /docs/en/application-note/AN12310.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Apr 27, 2022 645036621402383989 Application Note Y N Thermal Management Unit Usage 10 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 11 3 English This document provides recommendations for new designs based on the T1024, which is an advanced, multicore processor that combines two e5500 processor cores built on Power Architecture®, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. 1435612567420713656570 PSP 648.1 KB Registration without Disclaimer None documents Extended 1435612567420713656570 /secured/assets/documents/en/application-note/AN4971.pdf 648102 /secured/assets/documents/en/application-note/AN4971.pdf AN4971 documents Y N 2016-12-22 AN4971, QorIQ T1024 Family Design Checklist - Application Note /webapp/Download?colCode=AN4971&lang_cd=ja /secured/assets/documents/en/application-note/AN4971.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 18, 2018 645036621402383989 Application Note Y N AN4971, QorIQ T1024 Family Design Checklist - Application Note 12 0 English AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. 1523341236346699404047 PSP 10.9 MB Registration without Disclaimer None documents Extended 1523341236346699404047 /secured/assets/documents/en/application-note/AN12105.pdf 10918301 /secured/assets/documents/en/application-note/AN12105.pdf AN12105 documents Y N 2018-04-09 U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /webapp/Download?colCode=AN12105&lang_cd=ja /secured/assets/documents/en/application-note/AN12105.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 9, 2018 645036621402383989 Application Note Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 13 0 English Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. 1500885517617703401746 PSP 401.1 KB None None documents None 1500885517617703401746 /docs/en/application-note/AN4829.pdf 401068 /docs/en/application-note/AN4829.pdf AN4829 documents N N 2017-07-24 AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf /docs/en/application-note/AN4829.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 14 0 English Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. 1500876825316705874194 PSP 349.9 KB None None documents None 1500876825316705874194 /docs/en/application-note/AN5079.pdf 349919 /docs/en/application-note/AN5079.pdf AN5079 documents N N 2017-07-23 AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf /docs/en/application-note/AN5079.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 15 2 English AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. 1577097353709690091820 PSP 426.5 KB None None documents None 1577097353709690091820 /docs/en/application-note/AN5119.pdf 426530 /docs/en/application-note/AN5119.pdf AN5119 documents N N 2019-12-23 SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf /docs/en/application-note/AN5119.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 29, 2016 645036621402383989 Application Note Y N SerDes Configuration and Validation Tool Companion Application Note 16 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 17 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=ja /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 18 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 19 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 20 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 製品概要 Product Brief 1 21 0 English The QorIQ<sup>&#174;</sup> T1024/23 family of communications processors combines single or dual 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path&#13;&#10;acceleration architecture (DPAA) and network interfaces required for networking and telecommunications. 1428311117684711034035 PSP 199.8 KB Registration without Disclaimer None documents Extended 1428311117684711034035 /secured/assets/documents/en/product-brief/T1024PB.pdf 199819 /secured/assets/documents/en/product-brief/T1024PB.pdf T1024PB documents Y N 2015-04-06 T1024/14 and T1023/13 - Product Brief /webapp/Download?colCode=T1024PB&lang_cd=ja /secured/assets/documents/en/product-brief/T1024PB.pdf Product Brief N 899114358132306053 2023-06-18 pdf Y en Apr 5, 2015 899114358132306053 Product Brief Y N T1024/14 and T1023/13 - Product Brief サポート情報 Supporting Information 3 22 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 23 1 English 1475686550639726561333 PSP 18.5 KB None None documents None 1475686550639726561333 /docs/en/supporting-information/T1014_13-PECI.pdf 18486 /docs/en/supporting-information/T1014_13-PECI.pdf T1014_13-PECI documents N N 2016-11-09 T1014_13 Family Customer Export Control Information /docs/en/supporting-information/T1014_13-PECI.pdf /docs/en/supporting-information/T1014_13-PECI.pdf Supporting Information N 371282830530968666 2023-06-18 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N T1014_13 Family Customer Export Control Information 24 1 English 1475686548670717423236 PSP 18.5 KB None None documents None 1475686548670717423236 /docs/en/supporting-information/T1024_23-PECI.pdf 18477 /docs/en/supporting-information/T1024_23-PECI.pdf T1024_23-PECI documents N N 2016-11-09 T1024_23 Family Customer Export Control Information /docs/en/supporting-information/T1024_23-PECI.pdf /docs/en/supporting-information/T1024_23-PECI.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N T1024_23 Family Customer Export Control Information ホワイト・ペーパ White Paper 1 25 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper false 0 T1024 downloads ja true 1 Y PSP アプリケーション・ノート 12 /docs/en/application-note/AN12310.pdf 2022-04-27 1651046281017726871122 PSP 9 Apr 27, 2022 Application Note This application note introduces the LS1xxxx and LS2xxxx devices Thermal Management Unit (TMU). TMU Thermal Measurement Temperature Sensor Heat power None /docs/en/application-note/AN12310.pdf English documents 241590 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN12310.pdf Thermal Management Unit Usage /docs/en/application-note/AN12310.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Thermal Management Unit Usage 241.6 KB AN12310 N 1651046281017726871122 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 10 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /secured/assets/documents/en/application-note/AN4971.pdf 2016-12-22 1435612567420713656570 PSP 11 May 18, 2018 Application Note This document provides recommendations for new designs based on the T1024, which is an advanced, multicore processor that combines two e5500 processor cores built on Power Architecture®, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4971.pdf English documents 648102 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4971&lang_cd=ja AN4971, QorIQ T1024 Family Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4971.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N AN4971, QorIQ T1024 Family Design Checklist - Application Note 648.1 KB AN4971 N 1435612567420713656570 /secured/assets/documents/en/application-note/AN12105.pdf 2018-04-09 1523341236346699404047 PSP 12 Apr 9, 2018 Application Note AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12105.pdf English documents 10918301 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN12105&lang_cd=ja U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /secured/assets/documents/en/application-note/AN12105.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 10.9 MB AN12105 N 1523341236346699404047 /docs/en/application-note/AN4829.pdf 2017-07-24 1500885517617703401746 PSP 13 Jul 24, 2017 Application Note Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. None /docs/en/application-note/AN4829.pdf English documents 401068 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4829.pdf AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 401.1 KB AN4829 N 1500885517617703401746 /docs/en/application-note/AN5079.pdf 2017-07-23 1500876825316705874194 PSP 14 Jul 24, 2017 Application Note Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. None /docs/en/application-note/AN5079.pdf English documents 349919 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5079.pdf AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 349.9 KB AN5079 N 1500876825316705874194 /docs/en/application-note/AN5119.pdf 2019-12-23 1577097353709690091820 PSP 15 Jan 29, 2016 Application Note AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. None /docs/en/application-note/AN5119.pdf English documents 426530 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5119.pdf SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N SerDes Configuration and Validation Tool Companion Application Note 426.5 KB AN5119 N 1577097353709690091820 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 16 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 17 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=ja AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 18 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 19 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 20 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 サポート情報 3 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 22 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/T1014_13-PECI.pdf 2016-11-09 1475686550639726561333 PSP 23 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/T1014_13-PECI.pdf English documents 18486 None 371282830530968666 2023-06-18 N /docs/en/supporting-information/T1014_13-PECI.pdf T1014_13 Family Customer Export Control Information /docs/en/supporting-information/T1014_13-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N T1014_13 Family Customer Export Control Information 18.5 KB T1014_13-PECI N 1475686550639726561333 /docs/en/supporting-information/T1024_23-PECI.pdf 2016-11-09 1475686548670717423236 PSP 24 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/T1024_23-PECI.pdf English documents 18477 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/T1024_23-PECI.pdf T1024_23 Family Customer Export Control Information /docs/en/supporting-information/T1024_23-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N T1024_23 Family Customer Export Control Information 18.5 KB T1024_23-PECI N 1475686548670717423236 データ・シート 2 /secured/assets/documents/en/data-sheet/T1024.pdf 2015-07-23 1437668827017691600221 PSP 2 Dec 21, 2016 Data Sheet T1024 QorIQ advanced multicore processor combines two 64-bit ISA Power Architecture processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T1024.pdf English documents 3308150 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T1024&lang_cd=ja QorIQ T1024, T1014 Data Sheet /secured/assets/documents/en/data-sheet/T1024.pdf documents 980000996212993340 Data Sheet N en Extended pdf 1 Y N QorIQ T1024, T1014 Data Sheet 3.3 MB T1024 N 1437668827017691600221 /secured/assets/documents/en/data-sheet/T1023.pdf 2015-07-23 1437669029273714054537 PSP 3 Dec 21, 2016 Data Sheet T1023 QorIQ advanced multicore processor combines two 64-bit ISA Power Architecture processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T1023.pdf English documents 2947193 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T1023&lang_cd=ja QorIQ T1023, T1013 Data Sheet /secured/assets/documents/en/data-sheet/T1023.pdf documents 980000996212993340 Data Sheet N en Extended pdf 1 Y N QorIQ T1023, T1013 Data Sheet 2.9 MB T1023 N 1437669029273714054537 ファクト・シート 1 /docs/en/fact-sheet/T1024FS.pdf 2014-04-08 1396026129133725006112 PSP 1 Nov 4, 2015 Fact Sheet ファクト・シート QorIQ<sup>&#174;</sup>, T Series, T1 family, T1, T1023, T1013, T1024, T1014 None /docs/en/fact-sheet/T1024FS.pdf English 139002 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/T1024FS.pdf QorIQ<sup>&#174;</sup> T1024/14 and T1023/13 Communications Processors - Fact Sheet /docs/en/fact-sheet/T1024FS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 2 N N QorIQ<sup>&#174;</sup> T1024/14 and T1023/13 Communications Processors - Fact Sheet 139.0 KB T1024FS N 1396026129133725006112 ホワイト・ペーパ 1 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 25 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 リファレンス・マニュアル 5 /secured/assets/documents/en/reference-manual/T1024RM.pdf 2018-09-04 1433722816645718734966 PSP 4 Sep 5, 2018 Reference Manual The QorIQ<sup>&#174;</sup> T1024/23 family of communications processors combines single or dual 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network interfaces required for networking and telecommunications. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1024RM.pdf English documents 21449134 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1024RM&lang_cd=ja QorIQ T1024 Reference Manual /secured/assets/documents/en/reference-manual/T1024RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N QorIQ T1024 Reference Manual 21.4 MB T1024RM N 1433722816645718734966 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 2016-10-31 1233608188787709580857 PSP 5 May 3, 2018 Reference Manual This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. Registration without Disclaimer /secured/assets/documents/en/reference-manual/QEIWRM.pdf English documents 13369144 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=QEIWRM&lang_cd=ja QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /secured/assets/documents/en/reference-manual/QEIWRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 9 Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 13.4 MB QEIWRM N 1233608188787709580857 /secured/assets/documents/en/reference-manual/e5500RM.pdf 2011-11-07 1320675592951722488289 PSP 6 Jul 28, 2015 Reference Manual e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. Registration without Disclaimer /secured/assets/documents/en/reference-manual/e5500RM.pdf English documents 3661467 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=E5500RM&lang_cd=ja e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/e5500RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 3.7 MB E5500RM N 1320675592951722488289 /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf 2016-10-31 1437759164492730652137 PSP 7 Jul 24, 2015 Reference Manual T1024DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf English documents 16199184 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=T1024DPAARM&lang_cd=ja T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual /secured/assets/documents/en/reference-manual/T1024DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual 16.2 MB T1024DPAARM N 1437759164492730652137 /secured/assets/documents/en/reference-manual/T1024SECRM.pdf 2015-07-24 1437768398339710109264 PSP 8 Jul 24, 2015 Reference Manual T1024SECRM: This manual documents the T1024's security engine, the cryptographic acceleration and offloading hardware. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1024SECRM.pdf English documents 8037292 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1024SECRM&lang_cd=ja T1024SECRM, QorIQ<sup>&#174;</sup> T1024 Security (SEC) Reference Manual - Reference Manual /secured/assets/documents/en/reference-manual/T1024SECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1024SECRM, QorIQ<sup>&#174;</sup> T1024 Security (SEC) Reference Manual - Reference Manual 8.0 MB T1024SECRM N 1437768398339710109264 製品概要 1 /secured/assets/documents/en/product-brief/T1024PB.pdf 2015-04-06 1428311117684711034035 PSP 21 Apr 5, 2015 Product Brief The QorIQ<sup>&#174;</sup> T1024/23 family of communications processors combines single or dual 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path&#13;&#10;acceleration architecture (DPAA) and network interfaces required for networking and telecommunications. Registration without Disclaimer /secured/assets/documents/en/product-brief/T1024PB.pdf English documents 199819 None 899114358132306053 2023-06-18 Y /webapp/Download?colCode=T1024PB&lang_cd=ja T1024/14 and T1023/13 - Product Brief /secured/assets/documents/en/product-brief/T1024PB.pdf documents 899114358132306053 Product Brief N en Extended Y pdf 0 Y N T1024/14 and T1023/13 - Product Brief 199.8 KB T1024PB N 1428311117684711034035 true Y Products

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