QorIQ® P5040 | NXP Semiconductors

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QorIQ® P5040/5021 64-bit Dual- and Quad-Core Communications Processors

P5040 製造中止
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The QorIQ® P5 family delivers scalable, 64-bit processing with single-, dual-, and quad-core devices. With frequencies scaling up to 2.2 GHz, a tightly coupled cache hierarchy for low latency, and integrated hardware acceleration, the P5040 (quad-core) and P5021 (dual-core) devices are ideally suited for compute-intensive, power-conscious control plane applications.

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P5040 BD IMG

QorIQ P5040/5021 Processors
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Features

Core Complex

  • Four (P5040) or two (P5021) single-threaded e5500 cores built on Power Architecture® technology
  • Up to 2.2 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
  • Three levels of instruction: user, supervisor, hypervisor
  • Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture
  • 2.0 MB configures as dual 1 MB platform cache

Networking Elements

  • SerDes
    • 20 lanes at up to 5 Gbps
    • Supports SGMII, XAUI, PCI Express® (PCIe) rev1.1/2.0, SATA
  • Ethernet interfaces
    • Two 10 Gbps Ethernet MACs
    • Ten 1 Gbps Ethernet MACs

Accelerators and Memory Control

  • Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support
    • Up to 1600MT/s
  • DPAA incorporating acceleration for the following functions
    • Packet parsing, classification, and distribution (FMAN)
    • Queue management for scheduling, packet sequencing and congestion management (QMAN)
    • Hardware buffer management for buffer allocation and de-allocation (BMAN)
    • Cryptography acceleration (SEC 5.2) at up to 20Gbps
  • RAID 5 and 6 storage accelerator with support for end-to-end data protection information

Basic Peripherals and Interconnect

  • Three PCIe 2.0/3.0 controllers
  • Two serial ATA (SATA 2.0) controllers
  • Two high-speed USB 2.0 controllers with integrated PHY
  • Enhanced secure digital host controller (SD/MMC/eMMC)
  • Four I²C controllers
  • Two DUARTs
  • Integrated flash controller supporting NAND and NOR flash
  • Two 4-channel DMA engines

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
  • QorIQ® trust architecture 1.1
  • Secure boot, secure debug, tamper detection, volatile key storage

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比較表

P5040 P5021
Cores 4 2
Core Frequency 1.8 to 2.2 GHz 1.8 to 2.2 GHz
L2 Cache 512 KB 512 KB
L3/Platform Cache 2 MB 2 MB
DDR3 2x 64-bit 2x 64-bit
GbE 10x 1 GbE 2x 10 GbE 10x 1 GbE 2x 10 GbE
SERDES 20 Lanes 20 Lanes
Security Trust Trust

購入/パラメータ

1-10 の 25 結果

除外 25 NRND

パーツ

説明を表示

コンピュータ支援設計 モデル

状況

P5021NSE72QC
データ・シート

生産終了 (EOL)

P5021NSE7TMC
データ・シート

生産終了 (EOL)

P5021NSE7VNC
データ・シート

生産終了 (EOL)

P5021NSN72QC
データ・シート

生産終了 (EOL)

P5021NSN7TMC
データ・シート

生産終了 (EOL)

P5021NSN7VNC
データ・シート

生産終了 (EOL)

P5021NXE72QC
データ・シート

生産終了 (EOL)

P5021NXE7TMC
データ・シート

生産終了 (EOL)

P5021NXE7VNC
データ・シート

生産終了 (EOL)

P5021NXN72QC
データ・シート

生産終了 (EOL)

N true 0 PSPP5040ja 21 アプリケーション・ノート Application Note t789 8 カタログ Brochure t518 1 データ・シート Data Sheet t520 2 ファクト・シート Fact Sheet t523 1 ホワイト・ペーパ White Paper t530 2 ユーザ・ガイド User Guide t792 2 リファレンス・マニュアル Reference Manual t877 5 ja 3 1 1 English The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. 1316699641906701481590 PSP 758.9 KB None None documents None 1316699641906701481590 /docs/en/brochure/P2P3P5APPBRF.pdf 758908 /docs/en/brochure/P2P3P5APPBRF.pdf P2P3P5APPBRF N N 2016-10-31 QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf /docs/en/brochure/P2P3P5APPBRF.pdf Brochure N Y 712453003803778552 2022-12-07 pdf N en Sep 14, 2012 Brochure t518 カタログ Brochure N QorIQ P2040/P2041, P3 and P5 Series - Brochures 2 4 English The QorIQ<sup>&#174;</sup> P5 family delivers scalable 64-bit processing with single-, dual- and quad-core devices. With frequencies scaling up to 2.2 GHz, a tightly coupled cache hierarchy for low latency, and integrated hardware acceleration, the P5040 (quad-core) and P5021 (dual-core) devices are ideally suited for compute intensive, power-conscious control plane applications. 1335889907897714169956 PSP 127.6 KB None None documents None 1335889907897714169956 /docs/en/fact-sheet/P50405021FS.pdf 127592 /docs/en/fact-sheet/P50405021FS.pdf P50405021FS N N 2012-05-07 QorIQ<sup>&#174;</sup> P5040/P5021 Communications Processors - Fact Sheet /docs/en/fact-sheet/P50405021FS.pdf /docs/en/fact-sheet/P50405021FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en May 19, 2014 Fact Sheet t523 ファクト・シート Fact Sheet Y N QorIQ<sup>&#174;</sup> P5040/P5021 Communications Processors - Fact Sheet 3 0 English SEC is the chip's security engine module, which serves as Our latest cryptographic acceleration and offloading hardware. It combines functions previously implemented in separate modules to create a modular and scalable acceleration and assurance engine. It also implements block encryption algorithms, stream cipher algorithms, hashing algorithms, public key algorithms, run-time integrity checking, and a hardware random number generator. 1368215346180698531869 PSP 9.9 MB Registration without Disclaimer None documents Extended 1368215346180698531869 /secured/assets/documents/en/reference-manual/P5040SECRM.pdf 9945902 /secured/assets/documents/en/reference-manual/P5040SECRM.pdf P5040SECRM Y N 2013-05-10 P5040 Security (SEC) Reference Manual -Reference Manual /webapp/Download?colCode=P5040SECRM&docLang=en /secured/assets/documents/en/reference-manual/P5040SECRM.pdf Reference Manual N Y 500633505221135046 2023-06-18 pdf Y en May 11, 2013 Reference Manual t877 リファレンス・マニュアル Reference Manual Y N P5040 Security (SEC) Reference Manual -Reference Manual false ja ja データ・シート Data Sheet 2 4 Rev 1 English P5040: This document describes the electrical characteristics of the QorIQ<sup>&#174;</sup> P5040 integrated processor. 1387816682439714443306 PSP 2.7 MB Registration without Disclaimer None documents Extended 1387816682439714443306 /secured/assets/documents/en/data-sheet/P5040.pdf 2723338 /secured/assets/documents/en/data-sheet/P5040.pdf P5040 documents Y N 2013-12-23 QorIQ<sup>&#174;</sup> P5040 Data Sheet /webapp/Download?colCode=P5040&lang_cd=ja /secured/assets/documents/en/data-sheet/P5040.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en May 8, 2014 980000996212993340 Data Sheet Y N QorIQ<sup>&#174;</sup> P5040 Data Sheet 5 1 English P5021: This document describes the electrical characteristics of the P5021 QorIQ<sup>&#174;</sup> integrated processor. 1387816556031732356110 PSP 2.7 MB None None documents None 1387816556031732356110 /docs/en/data-sheet/P5021.pdf 2720867 /docs/en/data-sheet/P5021.pdf P5021 documents N N 2013-12-23 P5021, P5021 QorIQ<sup>&#174;</sup> Integrated Processor Data Sheet - Data Sheet /docs/en/data-sheet/P5021.pdf /docs/en/data-sheet/P5021.pdf Data Sheet N 980000996212993340 2022-12-07 pdf N en May 8, 2014 980000996212993340 Data Sheet Y N P5021, P5021 QorIQ<sup>&#174;</sup> Integrated Processor Data Sheet - Data Sheet リファレンス・マニュアル Reference Manual 4 6 3 English P5040RM: This manual describes the P5040 and P5021 QorIQ<sup>&#174;</sup> processors. 1371679341824725425442 PSP 17.5 MB Registration without Disclaimer None documents Extended 1371679341824725425442 /secured/assets/documents/en/reference-manual/P5040RM.pdf 17481045 /secured/assets/documents/en/reference-manual/P5040RM.pdf P5040RM documents Y N 2013-06-19 P5040RM, P5040 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Reference Manual with Updates - Reference Manual /webapp/Download?colCode=P5040RM&lang_cd=ja /secured/assets/documents/en/reference-manual/P5040RM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jul 11, 2016 500633505221135046 Reference Manual Y N P5040RM, P5040 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Reference Manual with Updates - Reference Manual 7 4 English e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. 1320675592951722488289 PSP 3.7 MB Registration without Disclaimer None documents Extended 1320675592951722488289 /secured/assets/documents/en/reference-manual/e5500RM.pdf 3661467 /secured/assets/documents/en/reference-manual/e5500RM.pdf E5500RM documents Y N 2011-11-07 e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /webapp/Download?colCode=E5500RM&lang_cd=ja /secured/assets/documents/en/reference-manual/e5500RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 28, 2015 500633505221135046 Reference Manual Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 8 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM&lang_cd=ja /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 9 2 English This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. 1301610099994679235703 PSP 19.4 MB Registration without Disclaimer None documents Extended 1301610099994679235703 /secured/assets/documents/en/reference-manual/DPAARM.pdf 19426366 /secured/assets/documents/en/reference-manual/DPAARM.pdf DPAARM documents Y N 2016-10-31 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /webapp/Download?colCode=DPAARM&lang_cd=ja /secured/assets/documents/en/reference-manual/DPAARM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Nov 4, 2011 500633505221135046 Reference Manual Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual アプリケーション・ノート Application Note 8 10 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 11 2 English AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. 1577097353709690091820 PSP 426.5 KB None None documents None 1577097353709690091820 /docs/en/application-note/AN5119.pdf 426530 /docs/en/application-note/AN5119.pdf AN5119 documents N N 2019-12-23 SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf /docs/en/application-note/AN5119.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 29, 2016 645036621402383989 Application Note Y N SerDes Configuration and Validation Tool Companion Application Note 12 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 13 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=ja /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 14 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 15 0 English This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. 1301697264409722558859 PSP 648.7 KB Registration without Disclaimer None documents Extended 1301697264409722558859 /secured/assets/documents/en/application-note/AN4290.pdf 648695 /secured/assets/documents/en/application-note/AN4290.pdf AN4290 documents Y N 2016-10-31 Configuring the Data Path Acceleration Architecture (DPAA) /webapp/Download?colCode=AN4290&lang_cd=ja /secured/assets/documents/en/application-note/AN4290.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 1, 2011 645036621402383989 Application Note N Configuring the Data Path Acceleration Architecture (DPAA) 16 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 17 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems ユーザ・ガイド User Guide 2 18 1 Y English https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y 1576719019599707128294 PSP None None documents None 1576719019599707128294 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC SPECTRE-MELTDOWN-POWER-ISA-DOC documents N N Y 2019-12-18 Spectre and Meltdown Updates for Power ISA Cores https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC User Guide N 132339537837198660 Y /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html 2022-12-07 N en Nov 14, 2019 132339537837198660 User Guide Y N Spectre and Meltdown Updates for Power ISA Cores 19 0 English P5040RDBUG: This document describes the P5040 and P5020 processors as the reference design board. 1369243938603698978714 PSP 1.9 MB None None documents None 1369243938603698978714 /docs/en/user-guide/P5040RDBUG.pdf 1872702 /docs/en/user-guide/P5040RDBUG.pdf P5040RDBUG documents N N 2016-10-31 P5040RDBUG, P5040 Reference Design Board User Guide - User Guide /docs/en/user-guide/P5040RDBUG.pdf /docs/en/user-guide/P5040RDBUG.pdf User Guide N 132339537837198660 2023-06-18 pdf N en May 22, 2013 132339537837198660 User Guide N P5040RDBUG, P5040 Reference Design Board User Guide - User Guide ホワイト・ペーパ White Paper 2 20 0 English In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. 1580452712610724357770 PSP 317.1 KB None None documents None 1580452712610724357770 /docs/en/white-paper/SPECTREPPCWP.pdf 317053 /docs/en/white-paper/SPECTREPPCWP.pdf SPECTREPPCWP documents N N 2020-01-30 Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf /docs/en/white-paper/SPECTREPPCWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jan 30, 2020 918633085541740938 White Paper Y N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 21 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper false 0 P5040 downloads ja true 1 Y PSP アプリケーション・ノート 8 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 10 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN5119.pdf 2019-12-23 1577097353709690091820 PSP 11 Jan 29, 2016 Application Note AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. None /docs/en/application-note/AN5119.pdf English documents 426530 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5119.pdf SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N SerDes Configuration and Validation Tool Companion Application Note 426.5 KB AN5119 N 1577097353709690091820 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 12 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 13 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=ja AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 14 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /secured/assets/documents/en/application-note/AN4290.pdf 2016-10-31 1301697264409722558859 PSP 15 Apr 1, 2011 Application Note This document describes how to initialize and configure some of the individual elements of the DPAA to send packets in and out of the device. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4290.pdf English documents 648695 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4290&lang_cd=ja Configuring the Data Path Acceleration Architecture (DPAA) /secured/assets/documents/en/application-note/AN4290.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Configuring the Data Path Acceleration Architecture (DPAA) 648.7 KB AN4290 N 1301697264409722558859 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 16 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 17 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 カタログ 1 /docs/en/brochure/P2P3P5APPBRF.pdf 2016-10-31 1316699641906701481590 PSP 1 Sep 14, 2012 Brochure カタログ The new QorIQ<sup>&#174;</sup> P2040/P2041 and P3041 processors expand the reach of NXP&#8217;s P4 platform into lower power applications. The P2040/P2041 and P3041 processors integrate four e500mc cores based on Power Architecture technology running up to 1.5 GHz within 12 watts. The new P5020 and P5010 processors offer NXP&#8217;s highest single-threaded performance for next-generation embedded control plane applications. With frequencies scaling to 2.2 GHz. None /docs/en/brochure/P2P3P5APPBRF.pdf English 758908 None Brochure 2022-12-07 N /docs/en/brochure/P2P3P5APPBRF.pdf QorIQ P2040/P2041, P3 and P5 Series - Brochures /docs/en/brochure/P2P3P5APPBRF.pdf documents 712453003803778552 Brochure N Y en None t518 pdf 1 N N QorIQ P2040/P2041, P3 and P5 Series - Brochures 758.9 KB P2P3P5APPBRF N 1316699641906701481590 データ・シート 2 /secured/assets/documents/en/data-sheet/P5040.pdf 2013-12-23 1387816682439714443306 PSP 4 May 8, 2014 Data Sheet P5040: This document describes the electrical characteristics of the QorIQ<sup>&#174;</sup> P5040 integrated processor. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P5040.pdf English documents 2723338 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=P5040&lang_cd=ja QorIQ<sup>&#174;</sup> P5040 Data Sheet /secured/assets/documents/en/data-sheet/P5040.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf Rev 1 Y N QorIQ<sup>&#174;</sup> P5040 Data Sheet 2.7 MB P5040 N 1387816682439714443306 /docs/en/data-sheet/P5021.pdf 2013-12-23 1387816556031732356110 PSP 5 May 8, 2014 Data Sheet P5021: This document describes the electrical characteristics of the P5021 QorIQ<sup>&#174;</sup> integrated processor. None /docs/en/data-sheet/P5021.pdf English documents 2720867 None 980000996212993340 2022-12-07 N /docs/en/data-sheet/P5021.pdf P5021, P5021 QorIQ<sup>&#174;</sup> Integrated Processor Data Sheet - Data Sheet /docs/en/data-sheet/P5021.pdf documents 980000996212993340 Data Sheet N en None Y pdf 1 N N P5021, P5021 QorIQ<sup>&#174;</sup> Integrated Processor Data Sheet - Data Sheet 2.7 MB P5021 N 1387816556031732356110 ファクト・シート 1 /docs/en/fact-sheet/P50405021FS.pdf 2012-05-07 1335889907897714169956 PSP 2 May 19, 2014 Fact Sheet ファクト・シート The QorIQ<sup>&#174;</sup> P5 family delivers scalable 64-bit processing with single-, dual- and quad-core devices. With frequencies scaling up to 2.2 GHz, a tightly coupled cache hierarchy for low latency, and integrated hardware acceleration, the P5040 (quad-core) and P5021 (dual-core) devices are ideally suited for compute intensive, power-conscious control plane applications. None /docs/en/fact-sheet/P50405021FS.pdf English 127592 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/P50405021FS.pdf QorIQ<sup>&#174;</sup> P5040/P5021 Communications Processors - Fact Sheet /docs/en/fact-sheet/P50405021FS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 4 N N QorIQ<sup>&#174;</sup> P5040/P5021 Communications Processors - Fact Sheet 127.6 KB P50405021FS N 1335889907897714169956 ホワイト・ペーパ 2 /docs/en/white-paper/SPECTREPPCWP.pdf 2020-01-30 1580452712610724357770 PSP 20 Jan 30, 2020 White Paper In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. None /docs/en/white-paper/SPECTREPPCWP.pdf English documents 317053 None 918633085541740938 2022-12-07 N /docs/en/white-paper/SPECTREPPCWP.pdf Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 317.1 KB SPECTREPPCWP N 1580452712610724357770 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 21 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 ユーザ・ガイド 2 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC 2019-12-18 https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y Y 1576719019599707128294 PSP 18 Nov 14, 2019 User Guide None /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC English Y documents Y None 132339537837198660 2022-12-07 N https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Spectre and Meltdown Updates for Power ISA Cores /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC documents 132339537837198660 User Guide N en None Y 1 N N Spectre and Meltdown Updates for Power ISA Cores SPECTRE-MELTDOWN-POWER-ISA-DOC N 1576719019599707128294 /docs/en/user-guide/P5040RDBUG.pdf 2016-10-31 1369243938603698978714 PSP 19 May 22, 2013 User Guide P5040RDBUG: This document describes the P5040 and P5020 processors as the reference design board. None /docs/en/user-guide/P5040RDBUG.pdf English documents 1872702 None 132339537837198660 2023-06-18 N /docs/en/user-guide/P5040RDBUG.pdf P5040RDBUG, P5040 Reference Design Board User Guide - User Guide /docs/en/user-guide/P5040RDBUG.pdf documents 132339537837198660 User Guide N en None pdf 0 N N P5040RDBUG, P5040 Reference Design Board User Guide - User Guide 1.9 MB P5040RDBUG N 1369243938603698978714 リファレンス・マニュアル 5 /secured/assets/documents/en/reference-manual/P5040RM.pdf 2013-06-19 1371679341824725425442 PSP 6 Jul 11, 2016 Reference Manual P5040RM: This manual describes the P5040 and P5021 QorIQ<sup>&#174;</sup> processors. Registration without Disclaimer /secured/assets/documents/en/reference-manual/P5040RM.pdf English documents 17481045 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=P5040RM&lang_cd=ja P5040RM, P5040 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/P5040RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 3 Y N P5040RM, P5040 QorIQ<sup>&#174;</sup> Integrated Multicore Communication Processor Reference Manual with Updates - Reference Manual 17.5 MB P5040RM N 1371679341824725425442 /secured/assets/documents/en/reference-manual/e5500RM.pdf 2011-11-07 1320675592951722488289 PSP 7 Jul 28, 2015 Reference Manual e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. Registration without Disclaimer /secured/assets/documents/en/reference-manual/e5500RM.pdf English documents 3661467 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=E5500RM&lang_cd=ja e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/e5500RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 3.7 MB E5500RM N 1320675592951722488289 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 8 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM&lang_cd=ja EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /secured/assets/documents/en/reference-manual/DPAARM.pdf 2016-10-31 1301610099994679235703 PSP 9 Nov 4, 2011 Reference Manual This manual describes the core set of DPAA functionality implemented in many QorIQ<sup>&#174;</sup> chips, and identifies those portions of the DPAA whose implementation varies from chip to chip. Registration without Disclaimer /secured/assets/documents/en/reference-manual/DPAARM.pdf English documents 19426366 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=DPAARM&lang_cd=ja QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual /secured/assets/documents/en/reference-manual/DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 2 Y N QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual 19.4 MB DPAARM N 1301610099994679235703 /secured/assets/documents/en/reference-manual/P5040SECRM.pdf 2013-05-10 1368215346180698531869 PSP 3 May 11, 2013 Reference Manual リファレンス・マニュアル SEC is the chip's security engine module, which serves as Our latest cryptographic acceleration and offloading hardware. It combines functions previously implemented in separate modules to create a modular and scalable acceleration and assurance engine. It also implements block encryption algorithms, stream cipher algorithms, hashing algorithms, public key algorithms, run-time integrity checking, and a hardware random number generator. Registration without Disclaimer /secured/assets/documents/en/reference-manual/P5040SECRM.pdf English 9945902 None Reference Manual 2023-06-18 Y /webapp/Download?colCode=P5040SECRM&docLang=en P5040 Security (SEC) Reference Manual -Reference Manual /secured/assets/documents/en/reference-manual/P5040SECRM.pdf documents 500633505221135046 Reference Manual N Y en Extended Y t877 pdf 0 Y N P5040 Security (SEC) Reference Manual -Reference Manual 9.9 MB P5040SECRM N 1368215346180698531869 true Y Products

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