Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
12NC: 935325449557
詳細
注文
パラメータ | 値 |
---|---|
Security Status | COMPANY PUBLIC |
Description | REV 1.1, 8610, 1.0V,-40C/105C |
パラメータ | 値 |
---|---|
Number of pins | 783 |
Package Style | BGA |
Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|---|
MC8610TPX1066JB(935325449557) | No | No | Yes | e0 | REACH SVHC | 3803.3 |
Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
---|---|---|---|---|---|---|---|
鉛はんだ | 鉛はんだ | 鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||
MC8610TPX1066JB (935325449557) | No | 3 | 245 | 245 | 30 | 30 |
Part/12NC | 関税分類番号(米国)免責事項: | 輸出規制品目番号(米国) |
---|---|---|
MC8610TPX1066JB (935325449557) | 854231 | 3A991A1 |
Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
---|---|---|---|---|
MC8610TPX1066JB (935325449557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
The MPC8610 processor is engineered to deliver breakthrough performance, connectivity and integration for embedded applications that process or display graphical images, such as kiosks, robotics, in-vehicle infotainment, cockpit displays, single-board computers and multi-function printers and scanners.
The MPC8610’s strength is its integration—the high-performance e600 core built on Power Architecture® technology—combined with the PowerQUICC® system-on-chip (SoC) platform and an LCD controller. With e600 core performance and integrated northbridge and southbridge functionality, the single chip replaces what could take up to four chips using other solutions. Moving all core-to-peripheral connections inside the device greatly reduces the number of high-speed parallel busses to be routed on the circuit board. This translates into smaller boards with fewer layers and higher processing density.