QorIQ® T1040 and T1020 Multicore Communications Processors | NXP Semiconductors

オートモーティブ

インダストリアル

コンスーマ

テクノロジ

QorIQ® T1040 and T1020 Multicore Communications Processors

T1040 アクティブ
NXP Priority Support: Helping You to Get to Market Faster

動画の上をクリックすると再生されます。

The QorIQ® T1040 quad-core and the T1020 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.

The T1040 and T1020 are the industry’s first 64-bit embedded processors with an integrated gigabit Ethernet switch. The T family is ideally suited for use in mixed control and data plane applications such as fixed routers, switches, integrated access devices, firewall and other packet filtering applications, as well as general-purpose embedded computing. Its high level of integration offers significant performance benefits and greatly helps to simplify hardware and software design.

The T1 family of devices is one of the industry’s most scalable, pin-compatible family of communications processors – and offers pin-compatible migration up to the higher-performance QorIQ T2081 device.

ブロック図

QorIQ T1040/20 and T1042/22 Communication Processors

QorIQ T1040/20 and T1042/22 Communication Processors
図を取得する PDF

Features

Core Complex

  • Two or four e5500 cores, built on Power Architecture technology
  • Up to 1.4 GHz with 64-bit ISA support
  • Three levels of instructions: user, supervisor, hypervisor
  • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
  • 256 KB backside L2 cache

Networking Elements

  • SerDes
    • Eight lanes at up to 5 Gbps
    • Supports SGMII, QSGMII, PCIe and SATA
  • Ethernet Interfaces
    • Eight-port Gigabit Ethernet switch

Accelerators and Memory Control

  • 32/64-bit DDR3L/4 SDRAM memory controller with ECC support
    • Up to 1600 MT/s
  • DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
    • Queue management for scheduling, packet sequencing and congestion management
    • Hardware buffer management for buffer allocation and de-allocation
    • Integrated security acceleration (SEC)
    • Signature detection (PME)
    • Up to five Gigabit Ethernet Interfaces

Basic Peripherals and Interconnect

  • CoreNet® platform cache
    • 256 KB shared platform cache
  • Hierarchical interconnect fabric
    • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
  • Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
    • Two high-speed USB 2.0 controllers with integrated PHYs
    • Enhanced secure digital host controller (SD/MMC/eMMC)
    • Enhanced serial peripheral interface (eSPI)
    • Two I²C controllers
    • Four UARTS
    • Integrated flash controller supporting NAND and NOR flash
  • DMA
    • Dual four channel
    • Up to 5x 1 Gbps Ethernet MACs as part of DPAA
  • QUICC Engine®
    • Support for legacy protocols TDM, HDLC, UART and ISDN
  • High-speed peripheral interfaces
    • Four PCI Express® 2.0 controllers

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
  • QorIQ® trust architecture
    • Secure boot, secure debug, tamper detection, volatile key storage
  • This product is included in our product longevity program, with assured supply for a minimum of 10 years after launch

もっと見る

比較表

T1020 T1022 T1040 T1042 T2081
CPU2 e55002 e55004 e55004 e55004 e6500 (dual-threaded)
Core Frequency1200-1400MHz1200-1400MHz1200-1400MHz1200-1400MHz1500-1800MHz
DDR I/F1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3L/4 to 1600MT/s1x DDR3/3L to 2133MT/s
Ethernet (with IEEE1588v2)8-Port GE Switch + 4x 1GE5x 1GE8-Port GE Switch + 4x 1GE5x 1GE2x 1/10GE + 6x 1GE
SERDES8 lanes (5GHz)8 lanes (5GHz)8 lanes (5GHz)8 lanes (5GHz)8 lanes (10GHz)
Package Pin Compatible

We recommend the following Quad Port Gigabit Copper EEE PHY

F104S8A F104X8A
Description QSGMII PHY Standard Temperature QSGMII PHY Extended Temperature
Operating Temperature (°C) 0 - 125 -40 - 125
Package Type 12x12, QFN, 138-pin, 0.65mm pin pitch 12x12, QFN, 138-pin, 0.65mm pin pitch
Read More Product Detail

購入/パラメータ

1-10 の 16 結果

マッチしていない 0 NRND

パーツ

説明を表示

注文

コンピュータ支援設計 モデル

状況

標準価格

パッケージタイプ

パッケージ端子数

コア：コア数 - 仕様

コア・タイプ

動作周波数[最大](MHz)

Junction Temperature (Min to Max) (℃)

L2 Cache (Max) (KB)

イーサネット・タイプ

PCIe

対応する外部メモリ

Typical Power

T1020NSE7MQB
データ・シート

アクティブ

100 @ US$74.22

FBGA780

780

2

e5500

1200

0 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

5

T1020NSE7PQB
データ・シート

アクティブ

100 @ US$89.07

FBGA780

780

2

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

5

T1020NSE7WQB
データ・シート

アクティブ

100 @ US$89.07

FBGA780

780

2

e5500

1500

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

5

T1020NSN7MQB
データ・シート

アクティブ

100 @ US$70.70

FBGA780

780

2

e5500

1200

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

5

T1020NSN7PQB
データ・シート

アクティブ

100 @ US$84.84

FBGA780

780

2

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

5

T1020NSN7WQB
データ・シート

アクティブ

100 @ US$84.84

FBGA780

780

2

e5500

1500

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

5

T1020NXE7MQB
データ・シート

アクティブ

100 @ US$85.35

FBGA780

780

2

e5500

1200

-40 to 105

256

10/100 BaseT, 1G, 2.5G

4

DDR3L SDRAM, DDR4 SDRAM

5

T1040NSE7MQB
データ・シート

アクティブ

100 @ US$82.50

FBGA780

780

4

e5500

1200

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

6

T1040NSE7PQB
データ・シート

アクティブ

100 @ US$98.99

FBGA780

780

4

e5500

1400

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

6

T1040NSE7WQB
データ・シート

アクティブ

100 @ US$98.99

FBGA780

780

4

e5500

1500

0 to 105

256

10/100 BaseT, 1G, 2.5G

—

DDR3L SDRAM, DDR4 SDRAM

4

N true 0 PSPT1040ja 28 アプリケーション・ノート Application Note t789 14 カタログ Brochure t518 1 サポート情報 Supporting Information t531 3 データ・シート Data Sheet t520 1 ファクト・シート Fact Sheet t523 1 ホワイト・ペーパ White Paper t530 2 リファレンス・マニュアル Reference Manual t877 5 製品概要 Product Brief t532 1 ja 1 1 1 Chinese 1349276610362740017554zh PSP 289.7 KB None None documents None 1349276610362740017554 /docs/zh/fact-sheet/T1FAMILYFS.pdf 289708 /docs/zh/fact-sheet/T1FAMILYFS.pdf T1FAMILYFS documents N N 2012-10-09 QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/zh/fact-sheet/T1FAMILYFS.pdf /docs/zh/fact-sheet/T1FAMILYFS.pdf /docs/zh/fact-sheet/T1FAMILYFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 N zh 736675474163315314 Fact Sheet N QorIQ<sup>®</sup> T系列T1020/22和T1040/42处理器 - 简介 2 English The QorIQ<sup>&#174;</sup> T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. 1349276610362740017554 PSP 289.7 KB None None documents None 1349276610362740017554 /docs/en/fact-sheet/T1FAMILYFS.pdf 289708 /docs/en/fact-sheet/T1FAMILYFS.pdf T1FAMILYFS N N 2012-10-09 QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/en/fact-sheet/T1FAMILYFS.pdf /docs/en/fact-sheet/T1FAMILYFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Feb 14, 2017 Fact Sheet t523 ファクト・シート Fact Sheet N QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet false ja ja データ・シート Data Sheet 1 2 2 English The T1040 QorIQ<sup>&#174;</sup> advanced multicore processor combines four 64-bit ISA Power Architecture&#8482; processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1422123003485724654459 PSP 1.5 MB Registration without Disclaimer None documents Extended 1422123003485724654459 /secured/assets/documents/en/data-sheet/T1040.pdf 1539278 /secured/assets/documents/en/data-sheet/T1040.pdf T1040 documents Y N 2015-01-24 QorIQ<sup>&#174;</sup> T1040, T1020 Data Sheet /webapp/Download?colCode=T1040&lang_cd=ja /secured/assets/documents/en/data-sheet/T1040.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Jun 29, 2015 980000996212993340 Data Sheet Y N QorIQ<sup>&#174;</sup> T1040, T1020 Data Sheet リファレンス・マニュアル Reference Manual 5 3 2 English The T1040 quad-core and T1020 dual-core QorIQ processor combines four or two 64-bit ISA Power Architecture® processor cores with high-performance DPAA, integrated 8-port Gigabit Ethernet switch and network peripheral bus interfaces required for networking and telecommunications. 1422074312466723542634 PSP 21.2 MB Registration without Disclaimer None documents Extended 1422074312466723542634 /secured/assets/documents/en/reference-manual/T1040RM.pdf 21193423 /secured/assets/documents/en/reference-manual/T1040RM.pdf T1040RM documents Y N 2017-03-06 QorIQ T1040 Reference Manual /webapp/Download?colCode=T1040RM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1040RM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jun 5, 2020 500633505221135046 Reference Manual Y N QorIQ T1040 Reference Manual 4 9 English This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. 1233608188787709580857 PSP 13.4 MB Registration without Disclaimer None documents Extended 1233608188787709580857 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 13369144 /secured/assets/documents/en/reference-manual/QEIWRM.pdf QEIWRM documents Y N 2016-10-31 QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /webapp/Download?colCode=QEIWRM&lang_cd=ja /secured/assets/documents/en/reference-manual/QEIWRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en May 3, 2018 500633505221135046 Reference Manual Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 5 4 English e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. 1320675592951722488289 PSP 3.7 MB Registration without Disclaimer None documents Extended 1320675592951722488289 /secured/assets/documents/en/reference-manual/e5500RM.pdf 3661467 /secured/assets/documents/en/reference-manual/e5500RM.pdf E5500RM documents Y N 2011-11-07 e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /webapp/Download?colCode=E5500RM&lang_cd=ja /secured/assets/documents/en/reference-manual/e5500RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 28, 2015 500633505221135046 Reference Manual Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 6 0 English T1040DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. 1422990991419695404861 PSP 18.4 MB Registration without Disclaimer None documents Extended 1422990991419695404861 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf 18442299 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf T1040DPAARM documents Y N 2016-10-31 T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual /webapp/Download?colCode=T1040DPAARM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Feb 3, 2015 500633505221135046 Reference Manual Y N T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual 7 0 English T1040SECRM: This manual documents the T1040's security engine, the cryptographic acceleration and offloading hardware. 1422046978213700573482 PSP 12.8 MB Registration without Disclaimer None documents Extended 1422046978213700573482 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf 12798684 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf T1040SECRM documents Y N 2015-01-23 T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual /webapp/Download?colCode=T1040SECRM&lang_cd=ja /secured/assets/documents/en/reference-manual/T1040SECRM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Jan 22, 2015 500633505221135046 Reference Manual Y N T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual アプリケーション・ノート Application Note 14 8 1 English This document provides guidelines for the handling and board mounting of FCBGA and FCCSP packages, including recommendations for printed-circuit board (PCB) design, soldering, and rework. It also includes recommendations for thermal solutions. 1662060818252696704548 PSP 6.5 MB None None documents None 1662060818252696704548 /docs/en/application-note/AN13656.pdf 6458358 /docs/en/application-note/AN13656.pdf AN13656 documents N N 2022-09-01 AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note /docs/en/application-note/AN13656.pdf /docs/en/application-note/AN13656.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 1, 2022 645036621402383989 Application Note Y N AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note 9 0 English This application note introduces the LS1xxxx and LS2xxxx devices Thermal Management Unit (TMU). TMU Thermal Measurement Temperature Sensor Heat power 1651046281017726871122 PSP 241.6 KB None None documents None 1651046281017726871122 /docs/en/application-note/AN12310.pdf 241590 /docs/en/application-note/AN12310.pdf AN12310 documents N N 2022-04-27 Thermal Management Unit Usage /docs/en/application-note/AN12310.pdf /docs/en/application-note/AN12310.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Apr 27, 2022 645036621402383989 Application Note Y N Thermal Management Unit Usage 10 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 11 0 English AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. 1523341236346699404047 PSP 10.9 MB Registration without Disclaimer None documents Extended 1523341236346699404047 /secured/assets/documents/en/application-note/AN12105.pdf 10918301 /secured/assets/documents/en/application-note/AN12105.pdf AN12105 documents Y N 2018-04-09 U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /webapp/Download?colCode=AN12105&lang_cd=ja /secured/assets/documents/en/application-note/AN12105.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 9, 2018 645036621402383989 Application Note Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 12 0 English Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. 1500885517617703401746 PSP 401.1 KB None None documents None 1500885517617703401746 /docs/en/application-note/AN4829.pdf 401068 /docs/en/application-note/AN4829.pdf AN4829 documents N N 2017-07-24 AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf /docs/en/application-note/AN4829.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 13 0 English Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. 1500876825316705874194 PSP 349.9 KB None None documents None 1500876825316705874194 /docs/en/application-note/AN5079.pdf 349919 /docs/en/application-note/AN5079.pdf AN5079 documents N N 2017-07-23 AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf /docs/en/application-note/AN5079.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 24, 2017 645036621402383989 Application Note N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 14 2 English AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. 1577097353709690091820 PSP 426.5 KB None None documents None 1577097353709690091820 /docs/en/application-note/AN5119.pdf 426530 /docs/en/application-note/AN5119.pdf AN5119 documents N N 2019-12-23 SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf /docs/en/application-note/AN5119.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 29, 2016 645036621402383989 Application Note Y N SerDes Configuration and Validation Tool Companion Application Note 15 1 English AN4825: This document provides recommendations for new designs based on the T1040, which is an advanced, multicore processor that combines four e5500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. 1422594417962727536636 PSP 862.5 KB Registration without Disclaimer documents Extended 1422594417962727536636 /secured/assets/documents/en/application-note/AN4825.pdf 862489 /secured/assets/documents/en/application-note/AN4825.pdf AN4825 documents Y N 2015-01-29 AN4825, T1040 Family Design Checklist - Application Note /webapp/Download?colCode=AN4825&lang_cd=ja /secured/assets/documents/en/application-note/AN4825.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 9, 2015 645036621402383989 Application Note N AN4825, T1040 Family Design Checklist - Application Note 16 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 17 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848&lang_cd=ja /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 18 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 19 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 20 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 21 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors カタログ Brochure 1 22 0 English The QorIQ<sup>&#174;</sup> communications portfolio delivers a smarter approach to multicore&#8212;providing a coherent migration path from single core to multicore and from 32-bit to 64-bit devices. 1400535710572713191513 PSP 1.4 MB None None documents None 1400535710572713191513 /docs/en/brochure/BRT1T2FAM.pdf 1381854 /docs/en/brochure/BRT1T2FAM.pdf BRT1T2FAM documents N N 2014-05-20 QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure /docs/en/brochure/BRT1T2FAM.pdf /docs/en/brochure/BRT1T2FAM.pdf Brochure N 712453003803778552 2022-12-07 pdf N en May 19, 2014 712453003803778552 Brochure Y N QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure 製品概要 Product Brief 1 23 0 English The T1040 QorIQ<sup>&#174;</sup> communication processor combines four 64-bit ISA Power architecture&#8482; processor cores with highperformance datapath acceleration logic, integrated 8-port Gigabit Ethernet switch, and network peripheral bus interfaces??required for networking, and telecommunications. 1396536601926689998231 PSP 222.3 KB Registration without Disclaimer None documents Extended 1396536601926689998231 /secured/assets/documents/en/product-brief/T1040PB.pdf 222276 /secured/assets/documents/en/product-brief/T1040PB.pdf T1040PB documents Y N 2014-04-03 T1040/20 and T1042/22 Product Brief /webapp/Download?colCode=T1040PB&lang_cd=ja /secured/assets/documents/en/product-brief/T1040PB.pdf Product Brief N 899114358132306053 2022-12-07 pdf Y en Apr 2, 2014 899114358132306053 Product Brief Y N T1040/20 and T1042/22 Product Brief サポート情報 Supporting Information 3 24 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 25 1 English 1475686549348735360890 PSP 18.0 KB None None documents None 1475686549348735360890 /docs/en/supporting-information/T1020_22-PECI.pdf 17965 /docs/en/supporting-information/T1020_22-PECI.pdf T1020_22-PECI documents N N 2016-11-09 T1020_22 Family Customer Export Control Information /docs/en/supporting-information/T1020_22-PECI.pdf /docs/en/supporting-information/T1020_22-PECI.pdf Supporting Information N 371282830530968666 2023-06-18 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N T1020_22 Family Customer Export Control Information 26 1 English 1475686547711729469962 PSP 18.0 KB None None documents None 1475686547711729469962 /docs/en/supporting-information/T1040_42-PECI.pdf 18035 /docs/en/supporting-information/T1040_42-PECI.pdf T1040_42-PECI documents N N 2016-11-09 T1040_42 Family Customer Export Control Information /docs/en/supporting-information/T1040_42-PECI.pdf /docs/en/supporting-information/T1040_42-PECI.pdf Supporting Information N 371282830530968666 2023-06-18 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N T1040_42 Family Customer Export Control Information ホワイト・ペーパ White Paper 2 27 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper 28 0 English In North America and Europe, the UL or CE marks are probably familiar sights in most households. Less widely known is that these marks stand for the stringent process that manufacturers must follow to qualify for those marks. 1375116135814736385332 PSP 472.0 KB None None documents None 1375116135814736385332 /docs/en/white-paper/MACHSAFETYPRODWP.pdf 471993 /docs/en/white-paper/MACHSAFETYPRODWP.pdf MACHSAFETYPRODWP documents N N 2016-10-31 Managing Machine Safety and Productivity with QorIQ Multicore Processors - White Paper /docs/en/white-paper/MACHSAFETYPRODWP.pdf /docs/en/white-paper/MACHSAFETYPRODWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Jul 29, 2013 918633085541740938 White Paper Y N Managing Machine Safety and Productivity with QorIQ Multicore Processors - White Paper false 0 T1040 downloads ja true 1 Y PSP アプリケーション・ノート 14 /docs/en/application-note/AN13656.pdf 2022-09-01 1662060818252696704548 PSP 8 Sep 1, 2022 Application Note This document provides guidelines for the handling and board mounting of FCBGA and FCCSP packages, including recommendations for printed-circuit board (PCB) design, soldering, and rework. It also includes recommendations for thermal solutions. None /docs/en/application-note/AN13656.pdf English documents 6458358 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13656.pdf AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note /docs/en/application-note/AN13656.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note 6.5 MB AN13656 N 1662060818252696704548 /docs/en/application-note/AN12310.pdf 2022-04-27 1651046281017726871122 PSP 9 Apr 27, 2022 Application Note This application note introduces the LS1xxxx and LS2xxxx devices Thermal Management Unit (TMU). TMU Thermal Measurement Temperature Sensor Heat power None /docs/en/application-note/AN12310.pdf English documents 241590 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN12310.pdf Thermal Management Unit Usage /docs/en/application-note/AN12310.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Thermal Management Unit Usage 241.6 KB AN12310 N 1651046281017726871122 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 10 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /secured/assets/documents/en/application-note/AN12105.pdf 2018-04-09 1523341236346699404047 PSP 11 Apr 9, 2018 Application Note AN12105: This document can be used to deploy U-Boot directly to the DDR of QorIQ T1040D4RDB using CodeWarrior and allows the user to initialize the board. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12105.pdf English documents 10918301 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN12105&lang_cd=ja U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note /secured/assets/documents/en/application-note/AN12105.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note 10.9 MB AN12105 N 1523341236346699404047 /docs/en/application-note/AN4829.pdf 2017-07-24 1500885517617703401746 PSP 12 Jul 24, 2017 Application Note Explains how to design a common board between T1024 and T1022 QorIQ communications processor by achieving hardware compatibility. None /docs/en/application-note/AN4829.pdf English documents 401068 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4829.pdf AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note /docs/en/application-note/AN4829.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note 401.1 KB AN4829 N 1500885517617703401746 /docs/en/application-note/AN5079.pdf 2017-07-23 1500876825316705874194 PSP 13 Jul 24, 2017 Application Note Provides comparison between QorIQ P1 series (P1010, P1020, P1022) and T1 series (T1024, T1014, T1023, T1013, T1040, T1020, T1042, T1022) devices. None /docs/en/application-note/AN5079.pdf English documents 349919 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5079.pdf AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note /docs/en/application-note/AN5079.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note 349.9 KB AN5079 N 1500876825316705874194 /docs/en/application-note/AN5119.pdf 2019-12-23 1577097353709690091820 PSP 14 Jan 29, 2016 Application Note AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. None /docs/en/application-note/AN5119.pdf English documents 426530 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5119.pdf SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N SerDes Configuration and Validation Tool Companion Application Note 426.5 KB AN5119 N 1577097353709690091820 /secured/assets/documents/en/application-note/AN4825.pdf 2015-01-29 1422594417962727536636 PSP 15 Apr 9, 2015 Application Note AN4825: This document provides recommendations for new designs based on the T1040, which is an advanced, multicore processor that combines four e5500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4825.pdf English documents 862489 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4825&lang_cd=ja AN4825, T1040 Family Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4825.pdf documents 645036621402383989 Application Note N en Extended pdf 1 Y N AN4825, T1040 Family Design Checklist - Application Note 862.5 KB AN4825 N 1422594417962727536636 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 16 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 17 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848&lang_cd=ja AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 18 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 19 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 20 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 21 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 カタログ 1 /docs/en/brochure/BRT1T2FAM.pdf 2014-05-20 1400535710572713191513 PSP 22 May 19, 2014 Brochure The QorIQ<sup>&#174;</sup> communications portfolio delivers a smarter approach to multicore&#8212;providing a coherent migration path from single core to multicore and from 32-bit to 64-bit devices. None /docs/en/brochure/BRT1T2FAM.pdf English documents 1381854 None 712453003803778552 2022-12-07 N /docs/en/brochure/BRT1T2FAM.pdf QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure /docs/en/brochure/BRT1T2FAM.pdf documents 712453003803778552 Brochure N en None Y pdf 0 N N QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure 1.4 MB BRT1T2FAM N 1400535710572713191513 サポート情報 3 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 24 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/T1020_22-PECI.pdf 2016-11-09 1475686549348735360890 PSP 25 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/T1020_22-PECI.pdf English documents 17965 None 371282830530968666 2023-06-18 N /docs/en/supporting-information/T1020_22-PECI.pdf T1020_22 Family Customer Export Control Information /docs/en/supporting-information/T1020_22-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N T1020_22 Family Customer Export Control Information 18.0 KB T1020_22-PECI N 1475686549348735360890 /docs/en/supporting-information/T1040_42-PECI.pdf 2016-11-09 1475686547711729469962 PSP 26 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/T1040_42-PECI.pdf English documents 18035 None 371282830530968666 2023-06-18 N /docs/en/supporting-information/T1040_42-PECI.pdf T1040_42 Family Customer Export Control Information /docs/en/supporting-information/T1040_42-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N T1040_42 Family Customer Export Control Information 18.0 KB T1040_42-PECI N 1475686547711729469962 データ・シート 1 /secured/assets/documents/en/data-sheet/T1040.pdf 2015-01-24 1422123003485724654459 PSP 2 Jun 29, 2015 Data Sheet The T1040 QorIQ<sup>&#174;</sup> advanced multicore processor combines four 64-bit ISA Power Architecture&#8482; processor cores with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T1040.pdf English documents 1539278 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T1040&lang_cd=ja QorIQ<sup>&#174;</sup> T1040, T1020 Data Sheet /secured/assets/documents/en/data-sheet/T1040.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 2 Y N QorIQ<sup>&#174;</sup> T1040, T1020 Data Sheet 1.5 MB T1040 N 1422123003485724654459 ファクト・シート 1 /docs/en/fact-sheet/T1FAMILYFS.pdf 2012-10-09 1349276610362740017554 PSP 1 Feb 14, 2017 Fact Sheet ファクト・シート The QorIQ<sup>&#174;</sup> T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture&#174; technology, with high-performance data path acceleration architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. None /docs/en/fact-sheet/T1FAMILYFS.pdf English 289708 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/T1FAMILYFS.pdf QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet /docs/en/fact-sheet/T1FAMILYFS.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 2 N N QorIQ T Series T1020/22 and T1040/42 Processors - Fact Sheet 289.7 KB T1FAMILYFS N 1349276610362740017554 ホワイト・ペーパ 2 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 27 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 /docs/en/white-paper/MACHSAFETYPRODWP.pdf 2016-10-31 1375116135814736385332 PSP 28 Jul 29, 2013 White Paper In North America and Europe, the UL or CE marks are probably familiar sights in most households. Less widely known is that these marks stand for the stringent process that manufacturers must follow to qualify for those marks. None /docs/en/white-paper/MACHSAFETYPRODWP.pdf English documents 471993 None 918633085541740938 2023-06-19 N /docs/en/white-paper/MACHSAFETYPRODWP.pdf Managing Machine Safety and Productivity with QorIQ Multicore Processors - White Paper /docs/en/white-paper/MACHSAFETYPRODWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Managing Machine Safety and Productivity with QorIQ Multicore Processors - White Paper 472.0 KB MACHSAFETYPRODWP N 1375116135814736385332 リファレンス・マニュアル 5 /secured/assets/documents/en/reference-manual/T1040RM.pdf 2017-03-06 1422074312466723542634 PSP 3 Jun 5, 2020 Reference Manual The T1040 quad-core and T1020 dual-core QorIQ processor combines four or two 64-bit ISA Power Architecture® processor cores with high-performance DPAA, integrated 8-port Gigabit Ethernet switch and network peripheral bus interfaces required for networking and telecommunications. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040RM.pdf English documents 21193423 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040RM&lang_cd=ja QorIQ T1040 Reference Manual /secured/assets/documents/en/reference-manual/T1040RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 2 Y N QorIQ T1040 Reference Manual 21.2 MB T1040RM N 1422074312466723542634 /secured/assets/documents/en/reference-manual/QEIWRM.pdf 2016-10-31 1233608188787709580857 PSP 4 May 3, 2018 Reference Manual This QEIWRM reference manual defines the functionality of the QUICC Engine<sup>&#174;</sup> block, a versatile RISC-based communication processor. The QUICC Engine block supports multiple external interfaces and protocols independently from the core processor in an integrated processing device. Use this reference manual in conjunction with your device reference manual to implement the QUICC Engine functionality. Registration without Disclaimer /secured/assets/documents/en/reference-manual/QEIWRM.pdf English documents 13369144 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=QEIWRM&lang_cd=ja QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual /secured/assets/documents/en/reference-manual/QEIWRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 9 Y N QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual 13.4 MB QEIWRM N 1233608188787709580857 /secured/assets/documents/en/reference-manual/e5500RM.pdf 2011-11-07 1320675592951722488289 PSP 5 Jul 28, 2015 Reference Manual e5500RM: This document includes the register model, instruction model, MMU, memory subsystem, debug and performance monitor facilities of the e5500. Registration without Disclaimer /secured/assets/documents/en/reference-manual/e5500RM.pdf English documents 3661467 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=E5500RM&lang_cd=ja e5500RM, e5500 Core Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/e5500RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N e5500RM, e5500 Core Reference Manual with Updates - Reference Manual 3.7 MB E5500RM N 1320675592951722488289 /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf 2016-10-31 1422990991419695404861 PSP 6 Feb 3, 2015 Reference Manual T1040DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf English documents 18442299 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040DPAARM&lang_cd=ja T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual /secured/assets/documents/en/reference-manual/T1040DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual 18.4 MB T1040DPAARM N 1422990991419695404861 /secured/assets/documents/en/reference-manual/T1040SECRM.pdf 2015-01-23 1422046978213700573482 PSP 7 Jan 22, 2015 Reference Manual T1040SECRM: This manual documents the T1040's security engine, the cryptographic acceleration and offloading hardware. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T1040SECRM.pdf English documents 12798684 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T1040SECRM&lang_cd=ja T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual /secured/assets/documents/en/reference-manual/T1040SECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual 12.8 MB T1040SECRM N 1422046978213700573482 製品概要 1 /secured/assets/documents/en/product-brief/T1040PB.pdf 2014-04-03 1396536601926689998231 PSP 23 Apr 2, 2014 Product Brief The T1040 QorIQ<sup>&#174;</sup> communication processor combines four 64-bit ISA Power architecture&#8482; processor cores with highperformance datapath acceleration logic, integrated 8-port Gigabit Ethernet switch, and network peripheral bus interfaces??required for networking, and telecommunications. Registration without Disclaimer /secured/assets/documents/en/product-brief/T1040PB.pdf English documents 222276 None 899114358132306053 2022-12-07 Y /webapp/Download?colCode=T1040PB&lang_cd=ja T1040/20 and T1042/22 Product Brief /secured/assets/documents/en/product-brief/T1040PB.pdf documents 899114358132306053 Product Brief N en Extended Y pdf 0 Y N T1040/20 and T1042/22 Product Brief 222.3 KB T1040PB N 1396536601926689998231 true Y Products

ドキュメント

クイック・リファレンス ドキュメンテーションの種類.

フィルタ

1-10 / 28 ドキュメント

コンパクトリスト

アプリケーション・ノート (14)
全て表示

デザイン・ファイル

クイック・リファレンス 設計・ファイルの種類.
フィルタ

1 設計・ファイル

ハードウェア

クイック・リファレンス ボードタイプ.
フィルタ

2 ハードウェア提供

ソフトウェア

クイック・リファレンス ソフトウェア・タイプ.

フィルタ

3 ソフトウェア・ファイル

注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。

エンジニアリング・サービス

4 エンジニアリング・サービス

この製品をサポートするその他のパートナー製品を見つけるには、当社の Web サイトにアクセスしてください パートナーマーケットプレイス.

トレーニング

フィルタ

2 トレーニング

サポート

お困りのことは何ですか？?

検索