Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
LQFP100: LQFP100, plastic, low profile quad flat package; 100 terminals; 0.5 mm pitch; 14 mm x 14 mm x 1.4 mm body
12NC: 935316523557
詳細
注文
パラメータ | 値 |
---|---|
Security Status | COMPANY PUBLIC |
Description | 16 BIT HYBRID CONTROLLER |
パラメータ | 値 |
---|---|
Number of pins | 100 |
Package Style | LQFP |
Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | 2次インターコネクト | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|---|
DSP56F826BU80E(935316523557) | Yes | Yes Certificate Of Analysis (CoA) | Yes | e3 | REACH SVHC | 650.4 |
Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | Maximum Time at Peak Temperatures (s) | |||
---|---|---|---|---|---|---|---|
鉛フリーはんだ | 鉛フリーはんだ | 鉛フリーはんだ | |||||
DSP56F826BU80E (935316523557) | No | 3 | 260 | 40 |
Part/12NC | 関税分類番号(米国)免責事項: | 輸出規制品目番号(米国) |
---|---|---|
DSP56F826BU80E (935316523557) | 854231 | 3A991A2 |
Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
---|---|---|---|---|
DSP56F826BU80E (935316523557) | 2025-04-16 | 2025-05-26 | 202504006I | Freescale Logo to NXP Logo Product Marking Conversion for All Remaining Former Freescale Products |
DSP56F826BU80E (935316523557) | 2020-12-15 | 2020-12-16 | 202011011I | NXP Will Add a Sealed Date to the Product Label |
The 56F826, a member of the 56800 core-based family of Digital Signal Controllers, combines the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals on a single chip. The 56F826 is ideal for a multitude of control, telephony and other applications requiring highly-integrated, high-performance solutions with all the flexibility enabled by Flash technology.
The 56800 core is based on a Harvard-style architecture consisting of three execution units which operate in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP- and MCU-style applications. The instruction set is also highly-efficient for C Compilers, enabling rapid development of optimized control applications.