Features
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
Package
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
Battery Cell Controller, Advanced, 6 Channels, TPL, LQFP48.
HLQFP48 LQFP64, plastic, low profile quad flat package; 64 terminals; 0.5 mm pitch; 10 mm x 10 mm x 1.4 mm body.
32-bit ARM Cortex-M3 flashless MCU with security features; 200 kB SRAM; Ethernet, two HS USB, EMC
12NC: 935305907551
詳細
注文
パラメータ | 値 |
---|---|
Operating Frequency [Max] (MHz) | 180 |
GPIO | 49 |
Ethernet | 1 |
USB Controllers | 2 |
USB (speed) | HS (2x) |
USB (type) | host/device |
CAN | 2 |
UART | 4 |
I2C | 2 |
SPI | 3 |
パラメータ | 値 |
---|---|
ADC (Channels) | 2 |
ADC (bits) | 10 |
ADC sample rate | 400 ksps |
Timers | 10 |
Timer (bits) | 32 |
SCTimer / PWM | 1 |
Temperature range | -40 °C to +85 °C |
Supply Voltage [min] (V) | 2.4 |
Supply Voltage [max] (V) | 3.6 |
Product category | 140-LPC1800- |
Part/12NC | 鉛フリー | EU RoHS | ハロゲンフリー | RHFインジケーター | REACH SVHC | Weight (mg) |
---|---|---|---|---|---|---|
LPC18S30FET100E(935305907551) | Yes | Yes Certificate Of Analysis (CoA) | Yes | REACH SVHC | 166.54298921 |
Part/12NC | 安全保障機能安全 | 吸湿感度レベル (MSL) | Peak Package Body Temperature (PPT) (C°) | ||
---|---|---|---|---|---|
鉛フリーはんだ | 鉛はんだ | 鉛フリーはんだ | |||
LPC18S30FET100E (935305907551) | No | 3 | 240 | 260 |
Part/12NC | 関税分類番号(米国)免責事項: | 輸出規制品目番号(米国) |
---|---|---|
LPC18S30FET100E (935305907551) | 854231 | 5A992 |
Part/12NC | 発行日 | 有効期限 | PCN | タイトル |
---|---|---|---|---|
LPC18S30FET100E (935305907551) | 2018-03-17 | 2018-06-25 | 201801009F01 | LPC18xx LPC43xx BGA Package Cu Wire Qualification for NXP-ATKH |
The LPC18S30FET100 is a Arm Cortex-M3 based microcontroller with security features for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC18S30FET100 operates at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18S30FET100 includes 200 kB of on-chip SRAM, security features with AES engine, a quad SPI Flash Interface (SPIFI), a State Configurable Timer/PWM (SCTimer/PWM) subsystem, two High-speed USB controllers, Ethernet, an external memory controller, and multiple digital and analog peripherals.