QorIQ® P4080/P4040/P4081 Multicore Communications Processors
デザイン・ファイル
完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.
QorIQ® P2040/P2041 Multicore Communications Processors with Data Path
- このページでは、新規設計を推奨しない製品に関する情報を掲載しています。
P2040 device is "Not recommended for new designs", please use the replacement families Power Architecture (T1040 ,T1042, T208x), Arm Architecture (LS1046).
The QorIQ® P2040 and P2041 quad-core processors bring high-end architectural features pioneered in the P4 platform into the low-end and mid-range quad-core space.
They are software-compatible with members of the P1 family and all devices in the P3, P4 and P5 families. This enables customers to scale software up and down the QorIQ product line. The P2040 and P2041 are pin-compatible, sharing a 23 x 23 mm package.
製品詳細
ブロック図
Features
Core Complex
- Quad e500mc cores to 1.2 GHz (P2040) and 1.5 GHz (P2041) with 32 KB I/D L1
- 128 KB L2 cache per core (P2041 only)
- CoreNet® fabric with 1 MB CoreNet platform cache
Networking Elements
- 10 SerDes lanes up to 5 GHz, supporting 3x PCI Express® 2.0, 2x Serial RapidIO® (1.3+2.1), 5x SGMII, 4x 2.5 Gb/s SGMII, XAUI (P2041 only), 2x Serial ATA 2.0, Aurora debug port
Accelerators and Memory Control
- 64-bit (72-bit with ECC) DDR3/3L memory controller to 1.2 GHz (P2040) and 1.3 GHz (P2041) data rate
- Hardware acceleration
- Frame manager for packet parsing, classification, and policing
- Queue manager for scheduling, and workload distribution
- Pattern matching engine for regular expression searches
- Security block for crypto algorithm acceleration
- RapidIO message manager for type nine and 11 messaging
Basic Peripherals and Interconnect
- SD/MMC, 2x DUART, 4x I²C, SPI, 2x RGMII, 2x USB 2.0 with integrated PHY, 16-bit local bus
- 783-pin FCPBGA package, 23 mm x 23 mm
Additional Features
- Hardware hypervisor for safe partitioning of operating systems between cores
- Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
比較表
| P2040 | P2041 | |
|---|---|---|
| Cores | 4 | 4 |
| Core Frequency | 667 to 1.2 GHz | 1.2 to 1.5 GHz |
| L2 Cache | - | 128 KB/core |
| L3/Platform Cache | 1 MB | 1 MB |
| DDR3 | 1x 32/64-bit | 1x 32/64-bit |
| GbE | - | 5x 1 Gigabit Ethernet 1x 10 Gigabit Ethernet |
| SERDES | 10 Lanes | 10 Lanes |
| Security | Trust | Trust |
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ドキュメント
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設計・リソース
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CodeWarrior Development Studio v10 for Power Architecture® Technology (Eclipse) EVAL注目
注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。
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