Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, Security, USB, QUICC Engine® with UTOPIA
デザイン・ファイル
完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.
Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, Security, USB, QUICC Engine®
The MPC8321 PowerQUICC® II Pro is part of the MPC8323E family of cost-effective network communication processors that meet the requirements of several small office/home office (SOHO), broadband access, routers and industrial control applications. It provides better CPU performance, additional functionality and faster interfaces than current PowerQUICC processors while addressing important time to market, price, power consumption and board real estate requirements.
Core Complex
The MPC8321 incorporates a unique configuration of the e300c2 (MPC603e-based) core. While this version of e300 core does not have a floating point unit (FPU), it has been designed to include dual integer units as well as a modified multiply instruction. These architectural enhancements enable more efficient operations to be executed in parallel, resulting in significant performance improvement. The core also includes 16 KB of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8321 includes a 32-bit PCI controller, four DMA channels, a flexible local bus and a 32-bit DDR-1/DDR-2 SDRAM memory controller.
QUICC Engine® Technology
A new single-reduced instruction set computing (RISC) version of the QUICC Engine communications engine forms the heart of the networking capability of the MPC8321. The QUICC Engine block contains several peripheral controllers and a single 32-bit RISC controller. Unique microcode packages provide support for network address port translation (NAPT), firewall, IPsec and advanced quality of service (QoS). Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). Each of the five UCCs can support a variety of communication protocols:
- Up to three 10/100 Mbps Ethernet
- High-level data link control (HDLC)
- Up to four time division multiplexing (TDM)
- Binary synchronous communications protocol (BISYNC)
- UCC can also support USB 2.0 (full/low-speed)
System Interface Unit
The MPC8321 family also includes a 32-bit double data rate (DDR)-1/DDR/2 memory controller, a 32-bit peripheral component interconnect (PCI) controller, a 16-bit local bus and four direct memory access (DMA) channels.
製品詳細
Features
- e300 core with dual integer units enables more efficient operations to be conducted in parallel, resulting in significant performance improvement
- The single-RISC QUICC Engine® communications block offers a future-proof solution for next-generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards
- DDR-1/DDR-2 memory controller—one 32-bit interface operating at up to 266 MHz supporting both DDR-1 and DDR-2
- Peripheral interfaces such as 32-bit, 66 MHz PCI, 16-bit, 66 MHz local bus interface and USB 2.0 (full/low-speed)
- High degree of software compatibility with previous-generation PowerQUICC® processor-based designs for backward compatibility and easier software migration
- This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch
比較表
PowerQUICC II Pro Family Comparison
| MPC8321 | MPC8321E | MPC8323 | MPC8323E | |
|---|---|---|---|---|
| Floating Point Unit | 0 | 0 | 0 | 0 |
| H/W Security | No | Sec 2.2 | No | Sec 2.2 |
| UTOPIA I/F (8-bit) | No | No | Yes | Yes |
| I²C | 1 | 1 | 1 | 1 |
| QMC Support | up to 64–ch @ 64kbps | up to 64–ch @ 64kbps | up to 64–ch @ 64kbps | up to 64–ch @ 64kbps |
| Memory Controller (no ECC) | 32-bit 266 MHz DDR1/DDR2 | 32-bit 266 MHz DDR1/DDR2 | 32-bit 266 MHz DDR1/DDR2 | 32-bit 266 MHz DDR1/DDR2 |
| QUICC Engine RISC Units | 1 | 1 | 1 | 1 |
| QUICC Engine Freq up | up to 200 MHz | up to 200 MHz | up to 200 MHz | up to 200 MHz |
| Ethernet | up to 3 - 10/100 | up to 3 - 10/100 | up to 3 - 10/100 | up to 3 - 10/100 |
| PCI | 32-bit up to 66 MHz | 32-bit up to 66 MHz | 32-bit up to 66 MHz | 32-bit up to 66 MHz |
| Local bus | 16-bit up to 66 MHz | 16-bit up to 66 MHz | 16-bit up to 66 MHz | 16-bit up to 66 MHz |
| UART | 2 | 2 | 2 | 2 |
| USB | USB 2.0 FS/LS | USB 2.0 FS/LS | USB 2.0 FS/LS | USB 2.0 FS/LS |
| L1 I/D Cache | 16KI/16KD | 16KI/16KD | 16KI/16KD | 16KI/16KD |
| Integer Units | 2 | 2 | 2 | 2 |
| TDM I/F | up to 4 – 32ch w/QMC | up to 4 – 32ch w/QMC | up to 4 – 32ch w/QMC | up to 4 – 32ch w/QMC |
| Package | 516-PBGA | 516-PBGA | 516-PBGA | 516-PBGA |
| Core Frequency | 266/333 | 266/333 | 266/333 | 266/333 |
| Core | e300c2 | e300c2 | e300c2 | e300c2 |
関連製品
Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, Security, USB, QUICC Engine® with UTOPIA
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ドキュメント
クイック・リファレンス ドキュメンテーションの種類.
1-5 の 26 ドキュメント
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データ・シート
MPC8323E Data Sheet
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リファレンス・マニュアル
Errata to MPC8323E Reference Manual, Rev. 2
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リファレンス・マニュアル
MPC8323E Reference Manual
設計・リソース
ハードウェア
クイック・リファレンス
ボードタイプ.
2 ハードウェア提供
-
エミュレータ、プローブ、プログラマPower Architecture® processor ( COP ) Probe Tips for CodeWarrior® TAP
-
エミュレータ、プローブ、プログラマCodeWarrior® TAP
ソフトウェア
クイック・リファレンス ソフトウェア・タイプ.
2 ソフトウェア・ファイル
-
設定ツール
UPM Tool for PowerQUICC® II Pro and PowerQUICC III Processors
注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。
エンジニアリング・サービス
NXPから直接サポートを受けるには、以下のサイトをご覧ください。 エンジニアリング・サービス.
2 エンジニアリング・サービス
-
インディペンデントデザインハウス (IDH)
トラステッド・アドバイザ・サービス
-
インディペンデントデザインハウス (IDH)
AndroidおよびLinuxエンジニアリングサポート
この製品をサポートするその他のパートナー製品を見つけるには、当社の Web サイトにアクセスしてください パートナーマーケットプレイス.
トレーニング
8 トレーニング
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オンデマンドウェビナー
INTEGRITY Training
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オンデマンドウェビナー
PHX-MPC83xx
-
オンデマンドウェビナー
Microware OS-9 RTOS insights
-
オンデマンドウェビナー
RTCS TCP/IP Stack
-
オンデマンドウェビナー
PHX-MPC832x
-
オンデマンドウェビナー
MQX RTOS
-
オンデマンドウェビナー
PHX-MPC8313
-
オンデマンドウェビナー
Custom Consultation