QorIQ® T2080 | NXP Semiconductors

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QorIQ® T2080 and T2081 Multicore Communications Processors

T2080 アクティブ
NXP Priority Support: Helping You to Get to Market Faster

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The 28 nm QorIQ T2080 and T2081 communications processors bring the architectural innovations of the T series flagship T4240, such as the 1.8 GHz dual-threaded e6500 core, into an eight virtual core mid-range platform at reduced power and price points.

The T2080 processor is primarily intended to succeed successful P3041 and P2041 mid-range series of quad-core devices as a control plane or integrated control and data plane processor. It provides an excellent migration path, as it offers 2x or better in core capability, cache size, SerDes bandwidth and Ethernet connectivity, within a similar power budget. It also provides a value-engineering opportunity for P4080 customers, as T2080 provides equivalent performance at much lower price and power.

The T2081 is a smaller-package version of the T2080, which is pin-compatible with the quad-core T1042. This provides T1042 customers an easy upgrade to higher performance if processing requirements increase. It also enables customers to reuse a single board for two different product performance levels.

ブロック図

T2080 BD IMG

QorIQ T2080 Communication Processor
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Features

Core Complex

  • Four dual-threaded e6500 cores built on Power Architecture® technology
    • Up to 1.8 GHz each, 6.0 DMIPS/MHz per core
    • Shares a 2 MB L2 cache
    • Three levels of instructions: User, supervisor, hypervisor
    • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
    • Advanced power management saving modes include state retention during power gating

Basic Peripherals and Interconnect

  • CoreNet® platform cache
  • Hierarchical interconnect fabric
    • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
  • Additional peripheral interfaces
    • Two high-speed USB 2.0 controllers with integrated PHYs
    • Enhanced secure digital host controller (SD/MMC/eMMC)
    • Enhanced serial peripheral interface (eSPI)
    • Four I²C controllers
    • Four UARTS
    • Integrated flash controller supporting NAND and NOR flash memory

Accelerators and Memory Controller

  • 64-bit DDR3/3L SDRAM memory controller with ECC support
    • Up to 2.1 GT/s
    • Memory pre-fetch engine
  • DPAA incorporating acceleration for the following functions
    • Packet parsing, classification and distribution up to 24Gb/s (FMAN)
    • Queue management for scheduling, packet sequencing and congestion management of up to 2^24 queues (QMAN)
    • Hardware buffer management for buffer allocation and de-allocation with 64 buffer pools (BMAN)
    • Integrated security acceleration (SEC) to 10 Gbps
    • Decompression/compression acceleration at up to 17.5 Gbps (DCE)
    • Signature detection (PME) to 10Gb/s
    • DPAA support of RapidIO® messaging (RMAN) (T2080 only)

Networking Elements

  • SerDes
    • 8 lanes at up to 10GHz
    • 8 lanes at up to 8GHz (T2080 only)
  • Ethernet interfaces: 8 MACS (7 on T2081) multiplexed over the following options
    • Up to four 10 Gb/s MACs supporting XFI/KR, XAUI, and HiGig (two on T2081 supporting XFI/KR only)
    • Up to eight SGMII (5 on T2080)
    • Up to four 2.5Gb/s SGMII
    • Up to two RGMII
  • High-speed peripheral interfaces
    • Two PCI Express 3.0 controllers (one on T2081)
    • Two PCI Express 2.0 controllers (three on T2081)
    • Endpoint SR-IOV
    • Two Serial RapidIO 2.1 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support (T2080 only)
    • Two Serial ATA (SATA) 2.0 controllers (T2080 only)
  • DMA
    • Dual eight channel

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
    • Logical to real address translation
    • Virtual core aware MMU/TLB
    • vMPIC (virtualized interrupt controller)/virtual core capable PPC cores
    • vDMA (user level DMA engine)
    • PAMUv2 (I/O MMU supporting paging)
    • DPAA (Ethernet MAC virtualization, accelerator virtualization)
  • Trust architecture secure boot
    • Secure boot, secure debug, tamper detection, volatile key storage, alternate image and key revocation
  • This product is included in our product longevity program, with assured supply for a minimum of 10 years after launch

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比較表

T2080 T2081
SerDes168
PCIe2x Gen3 + 2x Gen21x Gen3 + 3x Gen2
SRIO2 + RManNo
SATA2No
AuroraYesNo
10Gbps MACsUp to 4, with XFI, XAUI, and HiGigUp to 2 with XFI
1 Gbps MACsUp to 8Up to 7
Package25 x 25 mm , 896 pins, 0.8mm pitch23 x 23 mm, 780 pins, 0.8mm pitch, pin compatible with T1042

購入/パラメータ

1-10 の 49 結果

マッチしていない 0 NRND

パーツ

説明を表示

注文

コンピュータ支援設計 モデル

状況

標準価格

パッケージタイプ

パッケージ端子数

コア：コア数 - 仕様

コア・タイプ

動作周波数[最大](MHz)

Junction Temperature (Min to Max) (℃)

L2 Cache (Max) (KB)

L3 Cache (Max) (KB)

イーサネット・タイプ

PCIe

対応する外部メモリ

T2080NSE8MQB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1200

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3 SDRAM, DDR3L SDRAM, SDRAM

T2080NSE8MQLB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1200

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3L SDRAM

T2080NSE8P1B
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1533

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3L SDRAM

T2080NSE8PTB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1533

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3 SDRAM, DDR3L SDRAM, SDRAM

T2080NSE8T1B
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1800

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3L SDRAM

T2080NSE8TTB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1800

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3 SDRAM, DDR3L SDRAM, SDRAM

T2080NSN8MQB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1200

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3 SDRAM, DDR3L SDRAM, SDRAM

T2080NSN8MQLB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1200

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3L SDRAM

T2080NSN8P1B
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1533

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3L SDRAM

T2080NSN8PTB
データ・シート

アクティブ

—

FBGA896

896

8

e6500

1533

0 to 105

2000

512

RGMII, SGMII, XAUI

4

DDR3 SDRAM, DDR3L SDRAM, SDRAM

N true 0 PSPT2080ja 28 アプリケーション・ノート Application Note t789 14 カタログ Brochure t518 1 サポート情報 Supporting Information t531 2 データ・シート Data Sheet t520 2 ファクト・シート Fact Sheet t523 1 ホワイト・ペーパ White Paper t530 3 ユーザ・ガイド User Guide t792 1 リファレンス・マニュアル Reference Manual t877 3 製品概要 Product Brief t532 1 ja 1 1 1 Chinese 1349191150418724118794zh PSP 297.6 KB None None documents None 1349191150418724118794 /docs/zh/fact-sheet/T2080FS.pdf 297636 /docs/zh/fact-sheet/T2080FS.pdf T2080FS documents N N 2012-10-09 QorIQ T2080 and T2081 Communications Processors - Fact Sheet /docs/zh/fact-sheet/T2080FS.pdf /docs/zh/fact-sheet/T2080FS.pdf /docs/zh/fact-sheet/T2080FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 N zh 736675474163315314 Fact Sheet N QorIQ T2080和T2081通信处理器 - 简介 2 English The QorIQ<sup>&#174;</sup> T2080 and T2081 processors are based on the 64-bit e6500 core, built on Power Architecture&#174; technology, and run up to 1.8 GHz. They are targeted at mid-range control plane applications or mixed control and data plane applications. The highly efficient eight virtual core device achieves up to 1.8 GHz even while maintaining a short seven-stage pipeline for better latency response to unpredictable control plane code branches. 1349191150418724118794 PSP 297.6 KB None None documents None 1349191150418724118794 /docs/en/fact-sheet/T2080FS.pdf 297636 /docs/en/fact-sheet/T2080FS.pdf T2080FS N N 2012-10-09 QorIQ T2080 and T2081 Communications Processors - Fact Sheet /docs/en/fact-sheet/T2080FS.pdf /docs/en/fact-sheet/T2080FS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Feb 14, 2017 Fact Sheet t523 ファクト・シート Fact Sheet N QorIQ T2080 and T2081 Communications Processors - Fact Sheet false ja ja データ・シート Data Sheet 2 2 3 English The T2080 QorIQ<sup>&#174;</sup> integrated multicore communications processor combines 4 dualthreaded cores built on Power Architecture&#174; technology with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1422209548743718451102 PSP 1.9 MB Registration without Disclaimer None documents Extended 1422209548743718451102 /secured/assets/documents/en/data-sheet/T2080.pdf 1876725 /secured/assets/documents/en/data-sheet/T2080.pdf T2080 documents Y N 2018-03-06 QorIQ T2080 Data Sheet /webapp/Download?colCode=T2080&lang_cd=ja /secured/assets/documents/en/data-sheet/T2080.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Mar 7, 2018 980000996212993340 Data Sheet N QorIQ T2080 Data Sheet 3 3 English The T2081 QorIQ<sup>&#174;</sup> integrated multicore communications processor combines 4 dualthreaded cores built on Power Architecture&#174; technology with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. 1422209865312720804368 PSP 1.7 MB Registration without Disclaimer None documents Extended 1422209865312720804368 /secured/assets/documents/en/data-sheet/T2081.pdf 1656605 /secured/assets/documents/en/data-sheet/T2081.pdf T2081 documents Y N 2018-03-06 QorIQ T2081 Data Sheet /webapp/Download?colCode=T2081&lang_cd=ja /secured/assets/documents/en/data-sheet/T2081.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Mar 7, 2018 980000996212993340 Data Sheet N QorIQ T2081 Data Sheet リファレンス・マニュアル Reference Manual 3 4 4 English The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power Architecture® processor cores for a total of eight threads with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, data center, wireless infrastructure, and mil/aerospace applications. 1416843858892708470107 PSP 25.6 MB Registration without Disclaimer None documents Extended 1416843858892708470107 /secured/assets/documents/en/reference-manual/T2080RM.pdf 25573004 /secured/assets/documents/en/reference-manual/T2080RM.pdf T2080RM documents Y N 2016-12-12 QorIQ T2080 Reference Manual /webapp/Download?colCode=T2080RM&lang_cd=ja /secured/assets/documents/en/reference-manual/T2080RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Apr 19, 2021 500633505221135046 Reference Manual Y N QorIQ T2080 Reference Manual 5 0 English T2080DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. 1438975550253709811018 PSP 21.6 MB Registration without Disclaimer None documents Extended 1438975550253709811018 /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf 21585050 /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf T2080DPAARM documents Y N 2016-10-31 T2080DPAArm, QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual /webapp/Download?colCode=T2080DPAARM&lang_cd=ja /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Aug 7, 2015 500633505221135046 Reference Manual Y N T2080DPAArm, QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual 6 0 English T2080SECRM: The T2080 Security Reference Manual contains descriptions of the cryptographic modular and scalable acceleration and assurance engine, which implements block encryption algorithms, stream cipher algorithms, hashing algorithms, public key algorithms, run-time integrity checking, and a hardware NIST-compliant random number generation random number generator.?? 1416951123433713999383 PSP 12.2 MB Registration without Disclaimer None documents Extended 1416951123433713999383 /secured/assets/documents/en/reference-manual/T2080SECRM.pdf 12217228 /secured/assets/documents/en/reference-manual/T2080SECRM.pdf T2080SECRM documents Y N 2014-11-25 T2080SECRM, T2080 Security (SEC) Reference Manual with Updates - Reference Manual /webapp/Download?colCode=T2080SECRM&lang_cd=ja /secured/assets/documents/en/reference-manual/T2080SECRM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Aug 5, 2015 500633505221135046 Reference Manual Y N T2080SECRM, T2080 Security (SEC) Reference Manual with Updates - Reference Manual アプリケーション・ノート Application Note 14 7 1 English This document provides guidelines for the handling and board mounting of FCBGA and FCCSP packages, including recommendations for printed-circuit board (PCB) design, soldering, and rework. It also includes recommendations for thermal solutions. 1662060818252696704548 PSP 6.5 MB None None documents None 1662060818252696704548 /docs/en/application-note/AN13656.pdf 6458358 /docs/en/application-note/AN13656.pdf AN13656 documents N N 2022-09-01 AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note /docs/en/application-note/AN13656.pdf /docs/en/application-note/AN13656.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 1, 2022 645036621402383989 Application Note Y N AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note 8 4 English AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. 1567589575242748292636 PSP 194.6 KB None None documents None 1567589575242748292636 /docs/en/application-note/AN12572.pdf 194553 /docs/en/application-note/AN12572.pdf AN12572 documents N N 2019-09-04 Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf /docs/en/application-note/AN12572.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 26, 2021 645036621402383989 Application Note Y N Ethernet Backplane Driver Support Application Note 9 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 10 3 English AN4804: This document provides recommendations for new designs based on the T2080, which is an advanced, multicore processor that combines 4 dual-threaded e6500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. 1429130562730710816513 PSP 502.4 KB None None documents None 1429130562730710816513 /docs/en/application-note/AN4804.pdf 502363 /docs/en/application-note/AN4804.pdf AN4804 documents N N 2016-10-31 AN4804, QorIQ T2080 Design Checklist - Application Note /docs/en/application-note/AN4804.pdf /docs/en/application-note/AN4804.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 25, 2018 645036621402383989 Application Note N AN4804, QorIQ T2080 Design Checklist - Application Note 11 0 English AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. 1464124094029726989039 PSP 401.8 KB None None documents None 1464124094029726989039 /docs/en/application-note/AN5295.pdf 401764 /docs/en/application-note/AN5295.pdf AN5295 documents N N 2016-10-31 AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf /docs/en/application-note/AN5295.pdf Application Note N 645036621402383989 2022-12-07 pdf N en May 24, 2016 645036621402383989 Application Note N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 12 2 English AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. 1577097353709690091820 PSP 426.5 KB None None documents None 1577097353709690091820 /docs/en/application-note/AN5119.pdf 426530 /docs/en/application-note/AN5119.pdf AN5119 documents N N 2019-12-23 SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf /docs/en/application-note/AN5119.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jan 29, 2016 645036621402383989 Application Note Y N SerDes Configuration and Validation Tool Companion Application Note 13 Rev0 English AN5138: This application note describes a stimulation program which causes worst-case &#916;i/&#916;t events or load-step current changes. 1444169167915724456107 PSP 3.9 MB Registration without Disclaimer None documents Extended 1444169167915724456107 /secured/assets/documents/en/application-note/AN5138.pdf 3853692 /secured/assets/documents/en/application-note/AN5138.pdf AN5138 documents Y N 2015-10-06 AN5138, Implementing Maximum Load-Step (&#916;i/&#916;t) Software for T-Series Microprocessors - Application Note /webapp/Download?colCode=AN5138&lang_cd=ja /secured/assets/documents/en/application-note/AN5138.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Oct 6, 2015 645036621402383989 Application Note Y N AN5138, Implementing Maximum Load-Step (&#916;i/&#916;t) Software for T-Series Microprocessors - Application Note 14 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 15 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 16 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 17 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 18 0 English AN4786: This document explains how to download and use the functions of the Mentor Embedded Performance Library for AltiVec Technology (MEPL), which can be downloaded from the Mentor Graphics website. 1376599097877721043439 PSP 194.5 KB None None documents None 1376599097877721043439 /docs/en/application-note/AN4786.pdf 194531 /docs/en/application-note/AN4786.pdf AN4786 documents N N 2013-08-15 AN4786, MEPL Quick Start Guide - Application Note /docs/en/application-note/AN4786.pdf /docs/en/application-note/AN4786.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 15, 2013 645036621402383989 Application Note Y N AN4786, MEPL Quick Start Guide - Application Note 19 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 20 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors ユーザ・ガイド User Guide 1 21 1 Y English https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y 1576719019599707128294 PSP None None documents None 1576719019599707128294 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC SPECTRE-MELTDOWN-POWER-ISA-DOC documents N N Y 2019-12-18 Spectre and Meltdown Updates for Power ISA Cores https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC User Guide N 132339537837198660 Y /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html 2022-12-07 N en Nov 14, 2019 132339537837198660 User Guide Y N Spectre and Meltdown Updates for Power ISA Cores カタログ Brochure 1 22 0 English The QorIQ<sup>&#174;</sup> communications portfolio delivers a smarter approach to multicore&#8212;providing a coherent migration path from single core to multicore and from 32-bit to 64-bit devices. 1400535710572713191513 PSP 1.4 MB None None documents None 1400535710572713191513 /docs/en/brochure/BRT1T2FAM.pdf 1381854 /docs/en/brochure/BRT1T2FAM.pdf BRT1T2FAM documents N N 2014-05-20 QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure /docs/en/brochure/BRT1T2FAM.pdf /docs/en/brochure/BRT1T2FAM.pdf Brochure N 712453003803778552 2022-12-07 pdf N en May 19, 2014 712453003803778552 Brochure Y N QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure 製品概要 Product Brief 1 23 Rev 0 English T2080PB: This document briefly describes the T2080. 1397067766535714931498 PSP 726.2 KB None None documents None 1397067766535714931498 /docs/en/product-brief/T2080PB.pdf 726155 /docs/en/product-brief/T2080PB.pdf T2080PB documents N N 2014-04-09 T2080PB, T2080 Product Brief - Product Brief /docs/en/product-brief/T2080PB.pdf /docs/en/product-brief/T2080PB.pdf Product Brief N 899114358132306053 2023-06-19 pdf N en Apr 9, 2014 899114358132306053 Product Brief Y N T2080PB, T2080 Product Brief - Product Brief サポート情報 Supporting Information 2 24 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 25 1 English 1475686546939713866552 PSP 18.1 KB None None documents None 1475686546939713866552 /docs/en/supporting-information/T208X-PECI.pdf 18127 /docs/en/supporting-information/T208X-PECI.pdf T208X-PECI documents N N 2016-11-09 T208x Family Customer Export Control Information /docs/en/supporting-information/T208X-PECI.pdf /docs/en/supporting-information/T208X-PECI.pdf Supporting Information N 371282830530968666 2023-06-18 pdf N en Oct 5, 2016 371282830530968666 Supporting Information Y N T208x Family Customer Export Control Information ホワイト・ペーパ White Paper 3 26 0 English In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. 1580452712610724357770 PSP 317.1 KB None None documents None 1580452712610724357770 /docs/en/white-paper/SPECTREPPCWP.pdf 317053 /docs/en/white-paper/SPECTREPPCWP.pdf SPECTREPPCWP documents N N 2020-01-30 Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf /docs/en/white-paper/SPECTREPPCWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jan 30, 2020 918633085541740938 White Paper Y N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 27 0 English QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. 1419964678458711207150 PSP 1.4 MB None None documents None 1419964678458711207150 /docs/en/white-paper/QORIQPMWP.pdf 1418055 /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP documents N N 2017-03-30 QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf /docs/en/white-paper/QORIQPMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Mar 30, 2017 918633085541740938 White Paper N QORIQPMWP, QorIQ Power Management - White Paper 28 0 English This white paper demonstrates how to best architect software to leverage the DPAA hardware. 1338565191762730130183 PSP 1.1 MB None None documents None 1338565191762730130183 /docs/en/white-paper/QORIQDPAAWP.pdf 1051628 /docs/en/white-paper/QORIQDPAAWP.pdf QORIQDPAAWP documents N N 2016-10-31 QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf /docs/en/white-paper/QORIQDPAAWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jun 1, 2012 918633085541740938 White Paper Y N QorIQ DPAA Primer for Software Architecture false 0 T2080 downloads ja true 1 Y PSP アプリケーション・ノート 14 /docs/en/application-note/AN13656.pdf 2022-09-01 1662060818252696704548 PSP 7 Sep 1, 2022 Application Note This document provides guidelines for the handling and board mounting of FCBGA and FCCSP packages, including recommendations for printed-circuit board (PCB) design, soldering, and rework. It also includes recommendations for thermal solutions. None /docs/en/application-note/AN13656.pdf English documents 6458358 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13656.pdf AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note /docs/en/application-note/AN13656.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N AN13656: Assembly guidelines for Flip Chip plastic ball grid array and chip scale package Application Note 6.5 MB AN13656 N 1662060818252696704548 /docs/en/application-note/AN12572.pdf 2019-09-04 1567589575242748292636 PSP 8 Nov 26, 2021 Application Note AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. None /docs/en/application-note/AN12572.pdf English documents 194553 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12572.pdf Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf documents 645036621402383989 Application Note N en None Y pdf 4 N N Ethernet Backplane Driver Support Application Note 194.6 KB AN12572 N 1567589575242748292636 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 9 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN4804.pdf 2016-10-31 1429130562730710816513 PSP 10 Jan 25, 2018 Application Note AN4804: This document provides recommendations for new designs based on the T2080, which is an advanced, multicore processor that combines 4 dual-threaded e6500 processor cores built on Power Architecture&#174;, with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. None /docs/en/application-note/AN4804.pdf English documents 502363 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4804.pdf AN4804, QorIQ T2080 Design Checklist - Application Note /docs/en/application-note/AN4804.pdf documents 645036621402383989 Application Note N en None pdf 3 N N AN4804, QorIQ T2080 Design Checklist - Application Note 502.4 KB AN4804 N 1429130562730710816513 /docs/en/application-note/AN5295.pdf 2016-10-31 1464124094029726989039 PSP 11 May 24, 2016 Application Note AN5295: This application note outlines some common bring-up issues that customers may face when using the Serial RapidIO (SRIO) protocol on NXP QorIQ<sup>&#174;</sup> devices. The document covers issues related to device errata, hardware design, and software or configuration that may affect SRIO operation or performance. These guidelines aim to help with debugging problems and speed up the bring-up process. None /docs/en/application-note/AN5295.pdf English documents 401764 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5295.pdf AN5295, QorIQ Serial RapidIO Debug Tips - Application Note /docs/en/application-note/AN5295.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN5295, QorIQ Serial RapidIO Debug Tips - Application Note 401.8 KB AN5295 N 1464124094029726989039 /docs/en/application-note/AN5119.pdf 2019-12-23 1577097353709690091820 PSP 12 Jan 29, 2016 Application Note AN5119: This application note is a companion document to the SerDes Configuration & Validation Tool User Guide. It is provided to assist those engineers wishing to use the Tx Equalization, Built-In Self Test (BIST), and Jitter Scope test features of the QCVS SerDes validation tool. The 10 G SerDes block is the basis for describing the technical topics. The 10 G SerDes is in the T4240, B4860, T2080, P5040, and T1xx QorIQ multicore processors families. None /docs/en/application-note/AN5119.pdf English documents 426530 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5119.pdf SerDes Configuration and Validation Tool Companion Application Note /docs/en/application-note/AN5119.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N SerDes Configuration and Validation Tool Companion Application Note 426.5 KB AN5119 N 1577097353709690091820 /secured/assets/documents/en/application-note/AN5138.pdf 2015-10-06 1444169167915724456107 PSP 13 Oct 6, 2015 Application Note AN5138: This application note describes a stimulation program which causes worst-case &#916;i/&#916;t events or load-step current changes. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5138.pdf English documents 3853692 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5138&lang_cd=ja AN5138, Implementing Maximum Load-Step (&#916;i/&#916;t) Software for T-Series Microprocessors - Application Note /secured/assets/documents/en/application-note/AN5138.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev0 Y N AN5138, Implementing Maximum Load-Step (&#916;i/&#916;t) Software for T-Series Microprocessors - Application Note 3.9 MB AN5138 N 1444169167915724456107 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 14 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 15 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 16 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 17 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4786.pdf 2013-08-15 1376599097877721043439 PSP 18 Aug 15, 2013 Application Note AN4786: This document explains how to download and use the functions of the Mentor Embedded Performance Library for AltiVec Technology (MEPL), which can be downloaded from the Mentor Graphics website. None /docs/en/application-note/AN4786.pdf English documents 194531 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4786.pdf AN4786, MEPL Quick Start Guide - Application Note /docs/en/application-note/AN4786.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN4786, MEPL Quick Start Guide - Application Note 194.5 KB AN4786 N 1376599097877721043439 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 19 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 20 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 カタログ 1 /docs/en/brochure/BRT1T2FAM.pdf 2014-05-20 1400535710572713191513 PSP 22 May 19, 2014 Brochure The QorIQ<sup>&#174;</sup> communications portfolio delivers a smarter approach to multicore&#8212;providing a coherent migration path from single core to multicore and from 32-bit to 64-bit devices. None /docs/en/brochure/BRT1T2FAM.pdf English documents 1381854 None 712453003803778552 2022-12-07 N /docs/en/brochure/BRT1T2FAM.pdf QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure /docs/en/brochure/BRT1T2FAM.pdf documents 712453003803778552 Brochure N en None Y pdf 0 N N QorIQ<sup>&#174;</sup> T1 and T2 Families of Processors - Built for speed; designed to connect - Brochure 1.4 MB BRT1T2FAM N 1400535710572713191513 サポート情報 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 24 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/T208X-PECI.pdf 2016-11-09 1475686546939713866552 PSP 25 Oct 5, 2016 Supporting Information None /docs/en/supporting-information/T208X-PECI.pdf English documents 18127 None 371282830530968666 2023-06-18 N /docs/en/supporting-information/T208X-PECI.pdf T208x Family Customer Export Control Information /docs/en/supporting-information/T208X-PECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N T208x Family Customer Export Control Information 18.1 KB T208X-PECI N 1475686546939713866552 データ・シート 2 /secured/assets/documents/en/data-sheet/T2080.pdf 2018-03-06 1422209548743718451102 PSP 2 Mar 7, 2018 Data Sheet The T2080 QorIQ<sup>&#174;</sup> integrated multicore communications processor combines 4 dualthreaded cores built on Power Architecture&#174; technology with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T2080.pdf English documents 1876725 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T2080&lang_cd=ja QorIQ T2080 Data Sheet /secured/assets/documents/en/data-sheet/T2080.pdf documents 980000996212993340 Data Sheet N en Extended pdf 3 Y N QorIQ T2080 Data Sheet 1.9 MB T2080 N 1422209548743718451102 /secured/assets/documents/en/data-sheet/T2081.pdf 2018-03-06 1422209865312720804368 PSP 3 Mar 7, 2018 Data Sheet The T2081 QorIQ<sup>&#174;</sup> integrated multicore communications processor combines 4 dualthreaded cores built on Power Architecture&#174; technology with high-performance data path acceleration and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and military/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/data-sheet/T2081.pdf English documents 1656605 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=T2081&lang_cd=ja QorIQ T2081 Data Sheet /secured/assets/documents/en/data-sheet/T2081.pdf documents 980000996212993340 Data Sheet N en Extended pdf 3 Y N QorIQ T2081 Data Sheet 1.7 MB T2081 N 1422209865312720804368 ファクト・シート 1 /docs/en/fact-sheet/T2080FS.pdf 2012-10-09 1349191150418724118794 PSP 1 Feb 14, 2017 Fact Sheet ファクト・シート The QorIQ<sup>&#174;</sup> T2080 and T2081 processors are based on the 64-bit e6500 core, built on Power Architecture&#174; technology, and run up to 1.8 GHz. They are targeted at mid-range control plane applications or mixed control and data plane applications. The highly efficient eight virtual core device achieves up to 1.8 GHz even while maintaining a short seven-stage pipeline for better latency response to unpredictable control plane code branches. None /docs/en/fact-sheet/T2080FS.pdf English 297636 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/T2080FS.pdf QorIQ T2080 and T2081 Communications Processors - Fact Sheet /docs/en/fact-sheet/T2080FS.pdf documents 736675474163315314 Fact Sheet N Y en None t523 pdf 2 N N QorIQ T2080 and T2081 Communications Processors - Fact Sheet 297.6 KB T2080FS N 1349191150418724118794 ホワイト・ペーパ 3 /docs/en/white-paper/SPECTREPPCWP.pdf 2020-01-30 1580452712610724357770 PSP 26 Jan 30, 2020 White Paper In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. None /docs/en/white-paper/SPECTREPPCWP.pdf English documents 317053 None 918633085541740938 2022-12-07 N /docs/en/white-paper/SPECTREPPCWP.pdf Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 317.1 KB SPECTREPPCWP N 1580452712610724357770 /docs/en/white-paper/QORIQPMWP.pdf 2017-03-30 1419964678458711207150 PSP 27 Mar 30, 2017 White Paper QORIQPMWP: This document describes how Power Management technologies will play a more important role in controlling or reducing power consumption of electronic systems. None /docs/en/white-paper/QORIQPMWP.pdf English documents 1418055 None 918633085541740938 2023-06-19 N /docs/en/white-paper/QORIQPMWP.pdf QORIQPMWP, QorIQ Power Management - White Paper /docs/en/white-paper/QORIQPMWP.pdf documents 918633085541740938 White Paper N en None pdf 0 N N QORIQPMWP, QorIQ Power Management - White Paper 1.4 MB QORIQPMWP N 1419964678458711207150 /docs/en/white-paper/QORIQDPAAWP.pdf 2016-10-31 1338565191762730130183 PSP 28 Jun 1, 2012 White Paper This white paper demonstrates how to best architect software to leverage the DPAA hardware. None /docs/en/white-paper/QORIQDPAAWP.pdf English documents 1051628 None 918633085541740938 2022-12-07 N /docs/en/white-paper/QORIQDPAAWP.pdf QorIQ DPAA Primer for Software Architecture /docs/en/white-paper/QORIQDPAAWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N QorIQ DPAA Primer for Software Architecture 1.1 MB QORIQDPAAWP N 1338565191762730130183 ユーザ・ガイド 1 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC 2019-12-18 https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y Y 1576719019599707128294 PSP 21 Nov 14, 2019 User Guide None /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC English Y documents Y None 132339537837198660 2022-12-07 N https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Spectre and Meltdown Updates for Power ISA Cores /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC documents 132339537837198660 User Guide N en None Y 1 N N Spectre and Meltdown Updates for Power ISA Cores SPECTRE-MELTDOWN-POWER-ISA-DOC N 1576719019599707128294 リファレンス・マニュアル 3 /secured/assets/documents/en/reference-manual/T2080RM.pdf 2016-12-12 1416843858892708470107 PSP 4 Apr 19, 2021 Reference Manual The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power Architecture® processor cores for a total of eight threads with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, data center, wireless infrastructure, and mil/aerospace applications. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T2080RM.pdf English documents 25573004 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=T2080RM&lang_cd=ja QorIQ T2080 Reference Manual /secured/assets/documents/en/reference-manual/T2080RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 4 Y N QorIQ T2080 Reference Manual 25.6 MB T2080RM N 1416843858892708470107 /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf 2016-10-31 1438975550253709811018 PSP 5 Aug 7, 2015 Reference Manual T2080DPAArm: The QorIQ<sup>®</sup> data path acceleration architecture (DPAA) provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. Registration without Disclaimer /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf English documents 21585050 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T2080DPAARM&lang_cd=ja T2080DPAArm, QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual /secured/assets/documents/en/reference-manual/T2080DPAARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T2080DPAArm, QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual 21.6 MB T2080DPAARM N 1438975550253709811018 /secured/assets/documents/en/reference-manual/T2080SECRM.pdf 2014-11-25 1416951123433713999383 PSP 6 Aug 5, 2015 Reference Manual T2080SECRM: The T2080 Security Reference Manual contains descriptions of the cryptographic modular and scalable acceleration and assurance engine, which implements block encryption algorithms, stream cipher algorithms, hashing algorithms, public key algorithms, run-time integrity checking, and a hardware NIST-compliant random number generation random number generator.?? Registration without Disclaimer /secured/assets/documents/en/reference-manual/T2080SECRM.pdf English documents 12217228 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=T2080SECRM&lang_cd=ja T2080SECRM, T2080 Security (SEC) Reference Manual with Updates - Reference Manual /secured/assets/documents/en/reference-manual/T2080SECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N T2080SECRM, T2080 Security (SEC) Reference Manual with Updates - Reference Manual 12.2 MB T2080SECRM N 1416951123433713999383 製品概要 1 /docs/en/product-brief/T2080PB.pdf 2014-04-09 1397067766535714931498 PSP 23 Apr 9, 2014 Product Brief T2080PB: This document briefly describes the T2080. None /docs/en/product-brief/T2080PB.pdf English documents 726155 None 899114358132306053 2023-06-19 N /docs/en/product-brief/T2080PB.pdf T2080PB, T2080 Product Brief - Product Brief /docs/en/product-brief/T2080PB.pdf documents 899114358132306053 Product Brief N en None Y pdf Rev 0 N N T2080PB, T2080 Product Brief - Product Brief 726.2 KB T2080PB N 1397067766535714931498 true Y Products

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