LPC1857FET256|Arm Cortex-M3|32-bit MCU

The LPC185x/3x/2x/1x are Arm^® Cortex^®-M3 based microcontrollers for embedded applications. The Arm Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.

The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The Arm Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The Arm Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

The LPC185x/3x/2x/1x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.

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データシート

アプリケーション・ノート

製品詳細

Features

Processor core
- Arm Cortex-M3 processor, running at CPU frequencies of up to 180 MHz
- Arm Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions
- Arm Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
- Non-maskable Interrupt (NMI) input
- JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
- System tick timer
On-chip memory
- Up to 1 MB on-chip dual bank flash memory with flash accelerator
- 16 kB on-chip EEPROM data memory
- 136 kB SRAM for code and data use
- Multiple SRAM blocks with separate bus access
- 64 kB ROM containing boot code and on-chip software drivers
- 64 bit of One-Time Programmable (OTP) memory for general-purpose use
Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz
- 12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature and voltage (1 % accuracy for T_amb = 0 °C to 85 °C)
- Ultra-low power RTC crystal oscillator
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL
- Clock output
Configurable digital peripherals
- State Configurable Timer (SCT) subsystem on AHB
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCT, and ADC0/1
Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2)
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0)
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1)
- USB interface electrical test software included in ROM USB stack
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support
- One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to 1 Mbit/s
- One standard I²C-bus interface with monitor mode and standard I/O pins
- Two I²S interfaces with DMA support, each with one input and one output
Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices
- LCD controller with DMA support and a programmable display resolution of up to 1024H x 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping
- SD/MMC card interface
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB followers
- Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins
- Four general-purpose timer/counters with capture and match capabilities
- One motor control PWM for three-phase motor control
- One Quadrature Encoder Interface (QEI)
- Repetitive Interrupt timer (RI timer)
- Windowed watchdog timer
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers
- Event recorder with three inputs to record event identification and event time; can be battery powered
- Alarm timer; can be battery powered
Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight analog channels total. Each analog input is connected to both ADCs
Unique ID for each device
Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain
- RTC power domain can be powered separately by a 3 V battery supply
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain
- Brownout detect with four separate thresholds for interrupt and forced reset
- Power-On Reset (POR)
Available in LQFP208, LBGA256, LQFP144, and TFBGA100 packages

Target Applications

Industrial
Consumer
White goods
RFID readers
e-Metering

購入/パラメータ

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ドキュメント

クイック・リファレンスドキュメンテーションの種類.

1-5 の 28 ドキュメント

データ・シート
32-bit ARM Cortex-M3 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC

PDF改訂 5.3Feb 5, 20202.9 MBLPC185X_3X_2X_1X
アプリケーション・ノート
USBD Library for LPC4300/LPC1800 series MCUs

ZIP改訂 1.0Jul 9, 20188.6 MBTN00041
アプリケーション・ノート
Connecting TFT LCD with LCD controller of LPC MCU

ZIP改訂 1Aug 22, 20173.2 MBAN12027
アプリケーション・ノート
LPC1800 (with Flashless) Low Power Modes and Wake-up Times

ZIP改訂 1.0Aug 15, 20161.6 MBAN11853
アプリケーション・ノート
SCTimer/PWM cookbook

ZIP改訂 5.0Mar 22, 201625.5 MBAN11538, 中文
アプリケーション・ノート
LPC18xx Secondary USB Host bootloader

ZIP改訂 1.0Mar 6, 20153.7 MBAN11651
アプリケーション・ノート
Code Read Protection in LPC1800 and LPC4300

ZIP改訂 1.0Aug 14, 201416.6 MBAN11581
アプリケーション・ノート
Implementing PWM dithering on the LPC18xx SCTimer/PWM

ZIP改訂 1.0Aug 8, 20141.7 MBAN11580
アプリケーション・ノート
SCT camera interface design with LPC1800 and LPC4300

ZIP改訂 1.2Jun 12, 20141.4 MBAN11365
アプリケーション・ノート
AES encryption and decryption software on LPC microcontrollers

ZIP改訂 1.1Mar 17, 2014177.9 KBAN11241
アプリケーション・ノート
SDRAM interface to LPC18xx/43xx EMC

PDF改訂 1.0Jan 31, 2014351.0 KBAN11508
アプリケーション・ノート
Connecting a High Speed USB PHY via ULPI

ZIP改訂 1.0Aug 28, 2013366.1 KBAN11309
アプリケーション・ノート
LPC1800/LPC4300 One-Time Programmable (OTP) configuration

ZIP改訂 1.0Aug 23, 2013232.2 KBAN11292
アプリケーション・ノート
Wrting a flash programming algorithm for unsupported devices

ZIP改訂 1.0Aug 9, 2013398.5 KBAN11285
アプリケーション・ノート
Using SPIFI on LPC1800 and LPC4300

ZIP改訂 1.0Aug 9, 20137.2 MBAN11206
アプリケーション・ノート
In-System Programming of LPC18xx/43xx flash

ZIP改訂 1.0Aug 9, 2013426.8 KBAN11248
アプリケーション・ノート
Using SPIFI on LPC1850 Rev '-'

ZIP改訂 1.0Aug 9, 2013355.1 KBAN11080
アプリケーション・ノート
How to implement the PMBus software stack

ZIP改訂 1.0Jul 22, 20131.1 MBAN11318
アプリケーション・ノート
UUencoding for UART ISP

PDF改訂 1.0Jul 6, 2012142.1 KBAN11229
アプリケーション・ノート
PCB layout guidelines for NXP^® MCUs in BGA packages

PDF改訂 2.0Apr 22, 2011272.0 KBAN10778
ユーザ・ガイド
LPC18xx Arm^® Cortex^®-M3 microcontroller

PDF改訂 3.1Sep 13, 201911.9 MBUM10430

アカウントが必要です
カタログ
NXP^®'s Flexible camera interface

PDF改訂 1.0Mar 4, 2014910.0 KB75017537
エラッタ
Errata sheet LPC185x, LPC183x, LPC182x, LPC181x flash-based devices

PDF改訂 6.8Feb 5, 20201.0 MBES_LPC185X_3X_2X_1X_FLASH
パッケージ情報
plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm

PDF改訂 1.0Feb 8, 2016644.0 KBSOT740-2
レポートまたはプレゼンテーション
Driving LPC1700/LPC1800/LPC4300 with EPSON Crystals

PDF改訂 1.1Nov 27, 2015213.7 KBR_10076
サポート情報
ADC design guidelines

PDF改訂 1.0May 9, 2014148.8 KBTN00009
サポート情報
Connecting a USB power switch to the LPC18xx / LPC43xx

PDF改訂 1.0Mar 6, 201376.0 KBTN00007
サポート情報
LPC1800 and LPC4300 MxMEMMAP memory map

PDF改訂 1.0Dec 6, 2012148.0 KBTN00006

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設計・リソース

デザイン・ファイル

クイック・リファレンス設計・ファイルの種類.

5 設計・ファイル

完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.

シミュレーションとモデル
IBIS Model for LPC18xx and LPC43xx FET256-180-100

ZIP改訂 1Sep 12, 2017 17:21:00309.9 KBIBIS_LPC18xx_43xxFET256

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シミュレーションとモデル
BSDL for LPC18xx and LPC43xx

ZIP改訂 2Feb 27, 2018 11:57:00269.0 KBBSDL_LPC18XX_43XX

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IBIS Model_LPC18xx_LPC43xxFBD208

ZIP改訂 2Mar 25, 2020 16:19:00377.4 KBIBIS_LPC18xx_LPC43xxFBD208
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シンボルおよびフットプリント
LPC43xx/LPC18xx Eagle symbols

ZIP改訂 0Jun 3, 2016 00:00:0014.9 KBLPC43XX-EAGLE-SYM

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LPC18XX_43XX_SCH Orcad Symbols

ZIP改訂 1.0Apr 30, 2018 12:37:0052.2 KBLPC18XX_43XX_SCH_1

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