MPC8536E Communications Processors | NXP Semiconductors

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MPC8536E Communications Processors

MPC8536E
製造中止

  • MPC8536 device is "Not recommended for new designs", please use the replacement families Power Architecture (T1023, T1040 ,T1042), \n Arm Architecture (LS1023A).

The MPC8536E PowerQUICC® III is designed to deliver gigahertz-class complex application processing performance with advanced feature integration and high-speed connectivity for IP network and advanced media processing applications. It combines a robust e500 processor core, with enhanced peripherals and interconnect technology, to balance processor performance with I/O system throughput. The MPC8536E processor includes advanced energy management features that will enable next-generation embedded Internet media processing applications with energy efficiency levels under the environmental and governmental energy regulatory requirements.

The MPC8536E processor implements sophisticated power-saving modes for managing energy consumption in both dynamic and static power modes. Designers will be able to leverage these modes to efficiently match work accomplished with the correct level of energy consumed.

Access to the errata document for this device requires an NDA. Contact your local NXP® Sales Office or NXP Authorized Distributor.

ブロック図

NXP PowerQUIICC MPC8536E Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8536E Communications Processor Block Diagram

Features

  • e500 core, built on Power Architecture® technology, scaling up to 1.5 GHz
  • 32 KB I/D L1 cache
  • 512 KB L2 cache
  • 64-/32-bit DDR2/DDR3 memory controller up to 667 MHz data rate
  • Integrated security engine
    • DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
  • High-speed interconnects
    • 3 x PCI Express®
    • PCI
  • Advanced power management controller
  • 4 channel DMA controller
  • 2 x I²C
  • DUART
  • eSPI and enhanced local bus
  • GPIO
  • 2 x GbE with SGMII support
  • 3 x USB
  • 2 x SATA multiplexed with SGMII
  • SD/MMC interfaces
  • IEEE® 1588 support
  • 783-pin FC-PBGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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    N true 0 PSPMPC8536Eja 47 アプリケーション・ノート Application Note t789 28 アプリケーション・ノート・ソフトウェア Application Note Software t783 1 サポート情報 Supporting Information t531 2 データ・シート Data Sheet t520 1 パッケージ情報 Package Information t790 1 ファクト・シート Fact Sheet t523 5 ホワイト・ペーパ White Paper t530 3 リファレンス・マニュアル Reference Manual t877 5 製品概要 Product Brief t532 1 ja 4 1 7 English MPC8536EEC: This document describes the MPC8536E electrical characteristics. 1251864247798716085117 PSP 2.1 MB None None documents None 1251864247798716085117 /docs/en/data-sheet/MPC8536EEC.pdf 2075116 /docs/en/data-sheet/MPC8536EEC.pdf MPC8536EEC N N 2009-09-02 MPC8536EEC, MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications /docs/en/data-sheet/MPC8536EEC.pdf /docs/en/data-sheet/MPC8536EEC.pdf Data Sheet N Y 980000996212993340 2022-12-07 pdf N en Jul 23, 2015 Data Sheet t520 データ・シート Data Sheet Y N MPC8536EEC, MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications 2 0 English The MPC8536E is a new low-power, high-performance member of the PowerQUICC<sup>&#174;</sup> III&#8482; processor family that combines a computation-intensive super-scalar Power Architecture&#8482; processor core with high-performance system peripherals and advanced power management techniques to deliver high-performance computing in low-power envelopes required for imaging,&#13;&#10;communications, and industrial applications. 1221013098264726296700 PSP 517.4 KB None None documents None 1221013098264726296700 /docs/en/product-brief/MPC8536EPB.pdf 517384 /docs/en/product-brief/MPC8536EPB.pdf MPC8536EPB N 2008-09-09 MPC8536E Product Brief /docs/en/product-brief/MPC8536EPB.pdf /docs/en/product-brief/MPC8536EPB.pdf Product Brief N Y 899114358132306053 2022-12-07 pdf en Sep 9, 2008 Product Brief t532 製品概要 Product Brief Y N MPC8536E Product Brief 3 1 English The MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III integrated communications processor is designed to deliver gigahertz-class complex application processing performance with great feature integration and high-speed connectivity for IP network and advanced media processing applications. 1220581527222729487845 PSP 357.2 KB None None documents None 1220581527222729487845 /docs/en/fact-sheet/MPC8536EFS.pdf 357223 /docs/en/fact-sheet/MPC8536EFS.pdf MPC8536EFS N N 2016-10-31 MPC8536E Fact Sheet /docs/en/fact-sheet/MPC8536EFS.pdf /docs/en/fact-sheet/MPC8536EFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Jan 14, 2009 Fact Sheet t523 ファクト・シート Fact Sheet Y N MPC8536E Fact Sheet 4 1 English The MPC8536E integrates Power Architecture technology with system logic required for imaging, networking, and communications applications. The MPC8536E is a member of the PowerQUICC<sup>&#174;</sup> III&#8482; family of devices that combine system-level support for industry-standard interfaces with processors that implement Power Architecture technology. 1224106426497725579696 PSP 14.8 MB None None documents None 1224106426497725579696 /docs/en/reference-manual/MPC8536ERM.pdf 14772745 /docs/en/reference-manual/MPC8536ERM.pdf MPC8536ERM N N 2008-10-15 MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Reference Manual with Updates - Reference Manual /docs/en/reference-manual/MPC8536ERM.pdf /docs/en/reference-manual/MPC8536ERM.pdf Reference Manual N Y 500633505221135046 2024-12-15 pdf N en Aug 6, 2015 Reference Manual t877 リファレンス・マニュアル Reference Manual Y N MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Reference Manual with Updates - Reference Manual false ja ja リファレンス・マニュアル Reference Manual 4 5 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM&lang_cd=ja /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 6 1.2 English E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. 1152820363245707387417 PSP 117.9 KB None None documents None 1152820363245707387417 /docs/en/reference-manual/e500CORERMAD.pdf 117856 /docs/en/reference-manual/e500CORERMAD.pdf E500CORERMAD documents N N 2016-10-31 E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf /docs/en/reference-manual/e500CORERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf N en Sep 11, 2012 500633505221135046 Reference Manual N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 7 1.2 English This errata describes corrections to the MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Revision 1. For convenience, the section number and page number of the errata item in the reference manual are provided. 1261153896207726832875 PSP 535.7 KB None None documents None 1261153896207726832875 /docs/en/reference-manual/MPC8536ERMAD.pdf 535659 /docs/en/reference-manual/MPC8536ERMAD.pdf MPC8536ERMAD documents N 2009-12-18 Errata to MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8536ERMAD.pdf /docs/en/reference-manual/MPC8536ERMAD.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en Apr 15, 2010 500633505221135046 Reference Manual Y N Errata to MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Rev. 1 8 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual アプリケーション・ノート Application Note 28 9 0 Chinese Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203zh PSP 303.0 KB None None documents None 1641302649210707506203 /docs/zh/application-note/AN13461.pdf 302971 /docs/zh/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/zh/application-note/AN13461.pdf /docs/zh/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 zh May 9, 2022 645036621402383989 Application Note Y N 恩智浦微控制器故障排除清单 0 English Reviewing the troubleshoot microcontroller when there is a malfunction module. 1641302649210707506203 PSP 303.0 KB None None documents None 1641302649210707506203 /docs/en/application-note/AN13461.pdf 302971 /docs/en/application-note/AN13461.pdf AN13461 documents N N 2022-01-04 AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf /docs/en/application-note/AN13461.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2021 645036621402383989 Application Note Y N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 10 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645&lang_cd=ja /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 11 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 12 11 English AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. 1070297961506735248621 PSP 333.2 KB None None documents None 1070297961506735248621 /docs/en/application-note/AN2583.pdf 333170 /docs/en/application-note/AN2583.pdf AN2583 documents N N 2003-12-01 AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf /docs/en/application-note/AN2583.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jul 29, 2014 645036621402383989 Application Note Y N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 13 2 English AN3660SW.zip /docs/en/application-note-software/AN3660SW.zip /docs/en/application-note-software/AN3660SW.zip AN3660: This document provides recommendations for new designs based on the MPC8536E PowerQUICC<sup>&#174;</sup> III family of integrated host communications processors. 1235013658916701169172 PSP 1.4 MB None None documents None 1235013658916701169172 /docs/en/application-note/AN3660.pdf 1419665 /docs/en/application-note/AN3660.pdf AN3660 documents N N 2009-02-18 AN3660, MPC8536E PowerQUICC<sup>&#174;</sup> III - Application Notes /docs/en/application-note/AN3660.pdf /docs/en/application-note/AN3660.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 23, 2014 645036621402383989 Application Note Y N AN3660, MPC8536E PowerQUICC<sup>&#174;</sup> III - Application Notes 14 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 15 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940&lang_cd=ja /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 16 2 English This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. 1229718093838710459075 PSP 334.2 KB None None documents None 1229718093838710459075 /docs/en/application-note/AN3659.pdf 334243 /docs/en/application-note/AN3659.pdf AN3659 documents N N 2016-10-31 Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf /docs/en/application-note/AN3659.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 15, 2012 645036621402383989 Application Note N Booting from On-Chip ROM (eSDHC or eSPI) 17 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 18 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 19 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 20 1 English This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. 1225213465876727613770 PSP 828.9 KB None None documents None 1225213465876727613770 /docs/en/application-note/AN3649.pdf 828938 /docs/en/application-note/AN3649.pdf AN3649 documents N N 2016-10-31 Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf /docs/en/application-note/AN3649.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Apr 19, 2010 645036621402383989 Application Note Y N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 21 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 22 0 English AN4026SW.zip /secured/assets/documents/en/application-note-software/AN4026SW.zip /webapp/Download?colCode=AN4026SW&appType=license&docLang=en A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. 1260992898773711434436 PSP 718.0 KB None None documents None 1260992898773711434436 /docs/en/application-note/AN4026.pdf 718019 /docs/en/application-note/AN4026.pdf AN4026 documents N 2009-12-17 Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf /docs/en/application-note/AN4026.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2009 645036621402383989 Application Note N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 23 0 English High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e 1258066893562722616236 PSP 496.6 KB None None documents None 1258066893562722616236 /docs/en/application-note/AN3966.pdf 496625 /docs/en/application-note/AN3966.pdf AN3966 documents N 2016-10-31 PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf /docs/en/application-note/AN3966.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 10, 2009 645036621402383989 Application Note N PowerQUICC™ HDLC Support and Example Code 24 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 25 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646&lang_cd=ja /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 26 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869&lang_cd=ja /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 27 0 English This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. 1243968993550696784184 PSP 476.0 KB None None documents None 1243968993550696784184 /docs/en/application-note/AN3781.pdf 476033 /docs/en/application-note/AN3781.pdf AN3781 documents N 2010-05-11 Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf /docs/en/application-note/AN3781.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jun 2, 2009 645036621402383989 Application Note N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 28 1.0 English This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. 1208458263255715391554 PSP 505.7 KB None None documents None 1208458263255715391554 /docs/en/application-note/AN3550.pdf 505720 /docs/en/application-note/AN3550.pdf AN3550 documents N 2016-10-31 Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf /docs/en/application-note/AN3550.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 22, 2008 645036621402383989 Application Note N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 29 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 30 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 31 1 English The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. 1196114880779719950774 PSP 497.2 KB None None documents None 1196114880779719950774 /docs/en/application-note/AN3537.pdf 497175 /docs/en/application-note/AN3537.pdf AN3537 documents N 2016-10-31 Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf /docs/en/application-note/AN3537.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 6, 2007 645036621402383989 Application Note N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 32 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 33 0 English This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. 1194558645992741221612 PSP 574.8 KB None None documents None 1194558645992741221612 /docs/en/application-note/AN3533.pdf 574761 /docs/en/application-note/AN3533.pdf AN3533 documents N 2007-11-08 Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf /docs/en/application-note/AN3533.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 8, 2007 645036621402383989 Application Note Y N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 34 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 35 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 36 0 English This application note is a design guide to assist the customer in creating a low-layer, low-cost PCB design when using the MPC8536E device. 1224689525653726129043 PSP 1.4 MB None None documents None 1224689525653726129043 /docs/en/application-note/AN3444.pdf 1371873 /docs/en/application-note/AN3444.pdf AN3444 documents N 2008-10-22 A Strategy for Routing the MPC8536E in a Six-Layer PCB /docs/en/application-note/AN3444.pdf /docs/en/application-note/AN3444.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 1, 2007 645036621402383989 Application Note Y N A Strategy for Routing the MPC8536E in a Six-Layer PCB アプリケーション・ノート・ソフトウェア Application Note Software 1 37 0 English 1258066894053701788655 PSP 330.9 KB Registration With Click-Thru Software Licensing Agreement 1395958162559706127527 documents Extended 1258066894053701788655 /secured/assets/documents/en/application-note-software/AN3966SW.zip 330857 /secured/assets/documents/en/application-note-software/AN3966SW.zip AN3966SW documents Y N 2016-10-31 Software to accompany application note AN3966 /webapp/Download?colCode=AN3966SW&appType=license&lang_cd=ja /secured/assets/documents/en/application-note-software/AN3966SW.zip Application Note Software N 789425793691620447 2022-12-07 zip Y en Nov 10, 2009 789425793691620447 Application Note Software N Software to accompany application note AN3966 ファクト・シート Fact Sheet 4 38 0 English The MPC8536-ADK is a hardware and software platform for design engineers to quickly evaluate Android bytecode operation on the MPC8536E processor. 1256593241681716475433 PSP 1.8 MB None None documents None 1256593241681716475433 /docs/en/fact-sheet/MPC8536EADKFS.pdf 1796013 /docs/en/fact-sheet/MPC8536EADKFS.pdf MPC8536EADKFS documents N N 2020-02-12 MPC8536-ADK Platform for Android™ OS Evaluation on PowerQUICC® Processors /docs/en/fact-sheet/MPC8536EADKFS.pdf /docs/en/fact-sheet/MPC8536EADKFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Oct 26, 2009 736675474163315314 Fact Sheet Y N MPC8536-ADK Platform for Android™ OS Evaluation on PowerQUICC® Processors 39 1 English 1250885379567707412100 PSP 282.9 KB None None documents None 1250885379567707412100 /docs/en/fact-sheet/MPC8536RDKFS.pdf 282926 /docs/en/fact-sheet/MPC8536RDKFS.pdf MPC8536RDKFS documents N 2009-08-24 MPC8536RDK Fact Sheet /docs/en/fact-sheet/MPC8536RDKFS.pdf /docs/en/fact-sheet/MPC8536RDKFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf en Aug 21, 2009 736675474163315314 Fact Sheet Y N MPC8536RDK Fact Sheet 40 0 English NXP Semiconductors offers the low-power MPC8536E embedded media player reference design to help OEMs/ODMs jump start their time to market. This reference design outlines the comprehensive hardware and robust software applications which enable the quick addition of differentiating features prior to production. 1235155844472718031572 PSP 457.0 KB None None documents None 1235155844472718031572 /docs/en/fact-sheet/MPC8536RDFS.pdf 457022 /docs/en/fact-sheet/MPC8536RDFS.pdf MPC8536RDFS documents N N 2016-10-31 Digital Signage Media Player Reference Platform /docs/en/fact-sheet/MPC8536RDFS.pdf /docs/en/fact-sheet/MPC8536RDFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Feb 20, 2009 736675474163315314 Fact Sheet Y N Digital Signage Media Player Reference Platform 41 1 English The MPC8536E Development System (MPC8536DS) is ideal for hardware and software development for embedded applications. It leverages NXP&#8217;s highly integrated MPC8536E processor, built on Power Architecture&#174; technology, and leading-edge external components. 1220991869638694018953 PSP 294.2 KB None None documents None 1220991869638694018953 /docs/en/fact-sheet/MPC8536DSFS.pdf 294215 /docs/en/fact-sheet/MPC8536DSFS.pdf MPC8536DSFS documents N 2008-09-09 MPC8536DS Fact Sheet /docs/en/fact-sheet/MPC8536DSFS.pdf /docs/en/fact-sheet/MPC8536DSFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf en Jan 14, 2008 736675474163315314 Fact Sheet Y N MPC8536DS Fact Sheet パッケージ情報 Package Information 1 42 1 English This document is a presentation on understanding the FC-PBGA package. 1273780789511716723050 PSP 5.2 MB None None documents None 1273780789511716723050 /docs/en/package-information/FC-PBGAPRES.pdf 5219387 /docs/en/package-information/FC-PBGAPRES.pdf FC-PBGAPRES documents N N 2016-10-31 Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf /docs/en/package-information/FC-PBGAPRES.pdf Package Information N 302435339416912908 2022-12-07 pdf N en Jul 8, 2015 302435339416912908 Package Information N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation サポート情報 Supporting Information 2 43 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 44 1 English Customer Export Control Information Document 1232680177501710407693 PSP 21.4 KB None None documents None 1232680177501710407693 /docs/en/supporting-information/MPC8536EFAMPECI.pdf 21380 /docs/en/supporting-information/MPC8536EFAMPECI.pdf MPC8536EFAMPECI documents N N 2016-10-31 MPC8536 Family Customer Export Control Information /docs/en/supporting-information/MPC8536EFAMPECI.pdf /docs/en/supporting-information/MPC8536EFAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N MPC8536 Family Customer Export Control Information ホワイト・ペーパ White Paper 3 45 1 English The MPC8536E PowerQUICC<sup>&#174;</sup> III processor is a highly integrated system-on-chip (SoC) for green embedded computing applications. It supports low-power states nap, doze, sleep and deep sleep and incorporates advanced power management features to help OEM product developers meet government efficiency initiatives, such as ENERGY STAR, Top Runner and Energy Using Products (EuP). 1220998966117691846287 PSP 260.4 KB None None documents None 1220998966117691846287 /docs/en/white-paper/MPC8536EWP.pdf 260388 /docs/en/white-paper/MPC8536EWP.pdf MPC8536EWP documents N 2008-09-09 Green Embedded Computing and the MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III Processor /docs/en/white-paper/MPC8536EWP.pdf /docs/en/white-paper/MPC8536EWP.pdf White Paper N 918633085541740938 2023-06-19 pdf en Jun 18, 2009 918633085541740938 White Paper N N Green Embedded Computing and the MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III Processor 46 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP&lang_cd=ja /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance 47 0 English The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. 1208376896761708228520 PSP 735.3 KB None None documents None 1208376896761708228520 /docs/en/white-paper/DDRSDRAMWP.pdf 735286 /docs/en/white-paper/DDRSDRAMWP.pdf DDRSDRAMWP documents N N 2016-10-31 Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf /docs/en/white-paper/DDRSDRAMWP.pdf White Paper N 918633085541740938 2023-06-19 pdf N en Apr 16, 2008 918633085541740938 White Paper Y N Comparison of DDRx and SDRAM false 0 MPC8536E downloads ja true 1 Y PSP アプリケーション・ノート 28 /docs/en/application-note/AN13461.pdf 2022-01-04 1641302649210707506203 PSP 9 Nov 30, 2021 Application Note Reviewing the troubleshoot microcontroller when there is a malfunction module. None /docs/en/application-note/AN13461.pdf English documents 302971 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN13461.pdf AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note /docs/en/application-note/AN13461.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN13461: NXP Microcontroller Troubleshooting Checklist - Application Note 303.0 KB AN13461 N 1641302649210707506203 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 10 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645&lang_cd=ja SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 11 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /docs/en/application-note/AN2583.pdf 2003-12-01 1070297961506735248621 PSP 12 Jul 29, 2014 Application Note AN2583: This application note provides programming guidelines for the PowerQUICC<sup>&#174;</sup> DDR-SDRAM memory controller and specifically JEDEC-compatible DDR1 SDRAM memories. None /docs/en/application-note/AN2583.pdf English documents 333170 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN2583.pdf AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note /docs/en/application-note/AN2583.pdf documents 645036621402383989 Application Note N en None Y pdf 11 N N AN2583, Programming the PowerQUICC<sup>&#174;</sup> III/PowerQUICC II Pro DDR SDRAM Controller - Application Note 333.2 KB AN2583 N 1070297961506735248621 /docs/en/application-note/AN3660.pdf 2009-02-18 1235013658916701169172 PSP 13 Apr 23, 2014 Application Note AN3660: This document provides recommendations for new designs based on the MPC8536E PowerQUICC<sup>&#174;</sup> III family of integrated host communications processors. None /docs/en/application-note/AN3660.pdf English documents 1419665 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3660.pdf AN3660, MPC8536E PowerQUICC<sup>&#174;</sup> III - Application Notes /docs/en/application-note/AN3660.pdf documents 645036621402383989 Application Note N en None Y pdf 2 N N AN3660, MPC8536E PowerQUICC<sup>&#174;</sup> III - Application Notes 1.4 MB AN3660 N 1235013658916701169172 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 14 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 15 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940&lang_cd=ja AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN3659.pdf 2016-10-31 1229718093838710459075 PSP 16 Jun 15, 2012 Application Note This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. None /docs/en/application-note/AN3659.pdf English documents 334243 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3659.pdf Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf documents 645036621402383989 Application Note N en None pdf 2 N N Booting from On-Chip ROM (eSDHC or eSPI) 334.2 KB AN3659 N 1229718093838710459075 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 17 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 18 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 19 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3649.pdf 2016-10-31 1225213465876727613770 PSP 20 Apr 19, 2010 Application Note This application note explains the contents of the leader device tree in a multicore Hypervisor implementation used to allocate system resources to the individual partitions.&#13;&#10;Additionally, it describes the contents of the individual device trees that each partition uses for local allocation of those resources. None /docs/en/application-note/AN3649.pdf English documents 828938 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3649.pdf Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations /docs/en/application-note/AN3649.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations 828.9 KB AN3649 N 1225213465876727613770 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 21 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4026.pdf 2009-12-17 1260992898773711434436 PSP 22 Dec 17, 2009 Application Note A common use of the QUICC Engine block is to establish an HDLC communication path over a TDM interface, such as a T1 or E1 link. This application note describes the various sub-blocks used in the QUICC Engine communications engine for this application, discusses how the sub-blocks interoperate with each other, describes how to initialize them for the HDLC communication path, and provides a software demonstration of HDLC mode via a TDM interface using on-chip loopback. None /docs/en/application-note/AN4026.pdf English documents 718019 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4026.pdf Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC /docs/en/application-note/AN4026.pdf documents 645036621402383989 Application Note N en None pdf 0 N Communicating via HDLC over a TDM Interface with a QUICC Engine&#8482; UCC 718.0 KB AN4026 N 1260992898773711434436 /docs/en/application-note/AN3966.pdf 2016-10-31 1258066893562722616236 PSP 23 Nov 10, 2009 Application Note High-level data link control (HDLC) is widely used in the telecommunications and networking industries. NXP&#8217;s PowerQUICC&#8482; communications processors have extensive support for HDLC protocol through the communications processor module (CPM) and QUICC Engine&#8482; technologies.&#13;&#10;&#13;&#10;This application note explains how NXP&#8217;s existing&#13;&#10;PowerQUICC communications processors use the CPM and QUICC Engine technologies to support the HDLC protocol and provides HDLC e None /docs/en/application-note/AN3966.pdf English documents 496625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3966.pdf PowerQUICC™ HDLC Support and Example Code /docs/en/application-note/AN3966.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ HDLC Support and Example Code 496.6 KB AN3966 N 1258066893562722616236 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 24 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 25 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646&lang_cd=ja Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 26 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869&lang_cd=ja Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /docs/en/application-note/AN3781.pdf 2010-05-11 1243968993550696784184 PSP 27 Jun 2, 2009 Application Note This application note explains the procedures to utilize the extra FC (Flow Control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for the Power QUICC III&#8482; devices. None /docs/en/application-note/AN3781.pdf English documents 476033 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3781.pdf Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices /docs/en/application-note/AN3781.pdf documents 645036621402383989 Application Note N en None pdf 0 N Utilizing Extra FC Credits for PCI Express Inbound Posted Memory Write Transactions in PowerQUICC III&#8482; Devices 476.0 KB AN3781 N 1243968993550696784184 /docs/en/application-note/AN3550.pdf 2016-10-31 1208458263255715391554 PSP 28 Oct 22, 2008 Application Note This application note describes an example of how to use an external DMA engine with a Serial RapidIO&#174; interface. None /docs/en/application-note/AN3550.pdf English documents 505720 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3550.pdf Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology /docs/en/application-note/AN3550.pdf documents 645036621402383989 Application Note N en None pdf 1.0 N Using an External DMA Controller with Freescale Processors that Support Serial RapidIO® Technology 505.7 KB AN3550 N 1208458263255715391554 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 29 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 30 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3537.pdf 2016-10-31 1196114880779719950774 PSP 31 Dec 6, 2007 Application Note The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. None /docs/en/application-note/AN3537.pdf English documents 497175 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3537.pdf Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf documents 645036621402383989 Application Note N en None pdf 1 N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 497.2 KB AN3537 N 1196114880779719950774 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 32 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3533.pdf 2007-11-08 1194558645992741221612 PSP 33 Nov 8, 2007 Application Note This application note explains how to program one of the eLBC&#8217;s user-programmable machines (UPMs) to control an SDRAM memory device. None /docs/en/application-note/AN3533.pdf English documents 574761 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3533.pdf Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices /docs/en/application-note/AN3533.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices 574.8 KB AN3533 N 1194558645992741221612 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 34 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 35 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN3444.pdf 2008-10-22 1224689525653726129043 PSP 36 Oct 1, 2007 Application Note This application note is a design guide to assist the customer in creating a low-layer, low-cost PCB design when using the MPC8536E device. None /docs/en/application-note/AN3444.pdf English documents 1371873 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3444.pdf A Strategy for Routing the MPC8536E in a Six-Layer PCB /docs/en/application-note/AN3444.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N A Strategy for Routing the MPC8536E in a Six-Layer PCB 1.4 MB AN3444 N 1224689525653726129043 アプリケーション・ノート・ソフトウェア 1 /secured/assets/documents/en/application-note-software/AN3966SW.zip 2016-10-31 1258066894053701788655 PSP 37 Nov 10, 2009 Application Note Software Registration With Click-Thru Software Licensing Agreement /secured/assets/documents/en/application-note-software/AN3966SW.zip English documents 330857 1395958162559706127527 789425793691620447 2022-12-07 Y /webapp/Download?colCode=AN3966SW&appType=license&lang_cd=ja Software to accompany application note AN3966 /secured/assets/documents/en/application-note-software/AN3966SW.zip documents 789425793691620447 Application Note Software N en Extended zip 0 Y N Software to accompany application note AN3966 330.9 KB AN3966SW N 1258066894053701788655 サポート情報 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 43 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/MPC8536EFAMPECI.pdf 2016-10-31 1232680177501710407693 PSP 44 Dec 10, 2010 Supporting Information Customer Export Control Information Document None /docs/en/supporting-information/MPC8536EFAMPECI.pdf English documents 21380 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/MPC8536EFAMPECI.pdf MPC8536 Family Customer Export Control Information /docs/en/supporting-information/MPC8536EFAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1 N N MPC8536 Family Customer Export Control Information 21.4 KB MPC8536EFAMPECI N 1232680177501710407693 データ・シート 1 /docs/en/data-sheet/MPC8536EEC.pdf 2009-09-02 1251864247798716085117 PSP 1 Jul 23, 2015 Data Sheet データ・シート MPC8536EEC: This document describes the MPC8536E electrical characteristics. None /docs/en/data-sheet/MPC8536EEC.pdf English 2075116 None Data Sheet 2022-12-07 N /docs/en/data-sheet/MPC8536EEC.pdf MPC8536EEC, MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications /docs/en/data-sheet/MPC8536EEC.pdf documents 980000996212993340 Data Sheet N Y en None Y t520 pdf 7 N N MPC8536EEC, MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Hardware Specifications 2.1 MB MPC8536EEC N 1251864247798716085117 パッケージ情報 1 /docs/en/package-information/FC-PBGAPRES.pdf 2016-10-31 1273780789511716723050 PSP 42 Jul 8, 2015 Package Information This document is a presentation on understanding the FC-PBGA package. None /docs/en/package-information/FC-PBGAPRES.pdf English documents 5219387 None 302435339416912908 2022-12-07 N /docs/en/package-information/FC-PBGAPRES.pdf Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation /docs/en/package-information/FC-PBGAPRES.pdf documents 302435339416912908 Package Information N en None pdf 1 N N Flip Chip Plastic Ball Grid Array (FC-PBGA) Presentation 5.2 MB FC-PBGAPRES N 1273780789511716723050 ファクト・シート 5 /docs/en/fact-sheet/MPC8536EADKFS.pdf 2020-02-12 1256593241681716475433 PSP 38 Oct 26, 2009 Fact Sheet The MPC8536-ADK is a hardware and software platform for design engineers to quickly evaluate Android bytecode operation on the MPC8536E processor. None /docs/en/fact-sheet/MPC8536EADKFS.pdf English documents 1796013 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/MPC8536EADKFS.pdf MPC8536-ADK Platform for Android™ OS Evaluation on PowerQUICC® Processors /docs/en/fact-sheet/MPC8536EADKFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 0 N N MPC8536-ADK Platform for Android™ OS Evaluation on PowerQUICC® Processors 1.8 MB MPC8536EADKFS N 1256593241681716475433 /docs/en/fact-sheet/MPC8536RDKFS.pdf 2009-08-24 1250885379567707412100 PSP 39 Aug 21, 2009 Fact Sheet None /docs/en/fact-sheet/MPC8536RDKFS.pdf English documents 282926 None 736675474163315314 2022-12-07 /docs/en/fact-sheet/MPC8536RDKFS.pdf MPC8536RDK Fact Sheet /docs/en/fact-sheet/MPC8536RDKFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 1 N MPC8536RDK Fact Sheet 282.9 KB MPC8536RDKFS N 1250885379567707412100 /docs/en/fact-sheet/MPC8536RDFS.pdf 2016-10-31 1235155844472718031572 PSP 40 Feb 20, 2009 Fact Sheet NXP Semiconductors offers the low-power MPC8536E embedded media player reference design to help OEMs/ODMs jump start their time to market. This reference design outlines the comprehensive hardware and robust software applications which enable the quick addition of differentiating features prior to production. None /docs/en/fact-sheet/MPC8536RDFS.pdf English documents 457022 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/MPC8536RDFS.pdf Digital Signage Media Player Reference Platform /docs/en/fact-sheet/MPC8536RDFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 0 N N Digital Signage Media Player Reference Platform 457.0 KB MPC8536RDFS N 1235155844472718031572 /docs/en/fact-sheet/MPC8536DSFS.pdf 2008-09-09 1220991869638694018953 PSP 41 Jan 14, 2008 Fact Sheet The MPC8536E Development System (MPC8536DS) is ideal for hardware and software development for embedded applications. It leverages NXP&#8217;s highly integrated MPC8536E processor, built on Power Architecture&#174; technology, and leading-edge external components. None /docs/en/fact-sheet/MPC8536DSFS.pdf English documents 294215 None 736675474163315314 2022-12-07 /docs/en/fact-sheet/MPC8536DSFS.pdf MPC8536DS Fact Sheet /docs/en/fact-sheet/MPC8536DSFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 1 N MPC8536DS Fact Sheet 294.2 KB MPC8536DSFS N 1220991869638694018953 /docs/en/fact-sheet/MPC8536EFS.pdf 2016-10-31 1220581527222729487845 PSP 3 Jan 14, 2009 Fact Sheet ファクト・シート The MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III integrated communications processor is designed to deliver gigahertz-class complex application processing performance with great feature integration and high-speed connectivity for IP network and advanced media processing applications. None /docs/en/fact-sheet/MPC8536EFS.pdf English 357223 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/MPC8536EFS.pdf MPC8536E Fact Sheet /docs/en/fact-sheet/MPC8536EFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 1 N N MPC8536E Fact Sheet 357.2 KB MPC8536EFS N 1220581527222729487845 ホワイト・ペーパ 3 /docs/en/white-paper/MPC8536EWP.pdf 2008-09-09 1220998966117691846287 PSP 45 Jun 18, 2009 White Paper The MPC8536E PowerQUICC<sup>&#174;</sup> III processor is a highly integrated system-on-chip (SoC) for green embedded computing applications. It supports low-power states nap, doze, sleep and deep sleep and incorporates advanced power management features to help OEM product developers meet government efficiency initiatives, such as ENERGY STAR, Top Runner and Energy Using Products (EuP). None /docs/en/white-paper/MPC8536EWP.pdf English documents 260388 None 918633085541740938 2023-06-19 /docs/en/white-paper/MPC8536EWP.pdf Green Embedded Computing and the MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III Processor /docs/en/white-paper/MPC8536EWP.pdf documents 918633085541740938 White Paper N en None N pdf 1 N Green Embedded Computing and the MPC8536E PowerQUICC<sup>&#174;</sup>&#174; III Processor 260.4 KB MPC8536EWP N 1220998966117691846287 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 46 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP&lang_cd=ja Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 /docs/en/white-paper/DDRSDRAMWP.pdf 2016-10-31 1208376896761708228520 PSP 47 Apr 16, 2008 White Paper The focus of this white paper is to provide the end user with high level design considerations and/or trade-offs associated with migrating from SDRAM to DDR SDRAM-based designs. None /docs/en/white-paper/DDRSDRAMWP.pdf English documents 735286 None 918633085541740938 2023-06-19 N /docs/en/white-paper/DDRSDRAMWP.pdf Comparison of DDRx and SDRAM /docs/en/white-paper/DDRSDRAMWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Comparison of DDRx and SDRAM 735.3 KB DDRSDRAMWP N 1208376896761708228520 リファレンス・マニュアル 5 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 5 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM&lang_cd=ja EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /docs/en/reference-manual/e500CORERMAD.pdf 2016-10-31 1152820363245707387417 PSP 6 Sep 11, 2012 Reference Manual E500CORER: This errata document describes corrections to the PowerPC &#8482; e500 Core Family Reference Manual, Revision 1. None /docs/en/reference-manual/e500CORERMAD.pdf English documents 117856 None 500633505221135046 2022-12-07 N /docs/en/reference-manual/e500CORERMAD.pdf E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/e500CORERMAD.pdf documents 500633505221135046 Reference Manual N en None pdf 1.2 N N E500CORER, Errata to PowerPC ™ e500 Core Family - Reference Manual 117.9 KB E500CORERMAD N 1152820363245707387417 /docs/en/reference-manual/MPC8536ERMAD.pdf 2009-12-18 1261153896207726832875 PSP 7 Apr 15, 2010 Reference Manual This errata describes corrections to the MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Revision 1. For convenience, the section number and page number of the errata item in the reference manual are provided. None /docs/en/reference-manual/MPC8536ERMAD.pdf English documents 535659 None 500633505221135046 2022-12-07 /docs/en/reference-manual/MPC8536ERMAD.pdf Errata to MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Rev. 1 /docs/en/reference-manual/MPC8536ERMAD.pdf documents 500633505221135046 Reference Manual N en None Y pdf 1.2 N Errata to MPC8536E PowerQUICC<sup>&#174;</sup> III&#8482; Integrated Processor Reference Manual, Rev. 1 535.7 KB MPC8536ERMAD N 1261153896207726832875 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 8 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB /docs/en/reference-manual/MPC8536ERM.pdf 2008-10-15 1224106426497725579696 PSP 4 Aug 6, 2015 Reference Manual リファレンス・マニュアル The MPC8536E integrates Power Architecture technology with system logic required for imaging, networking, and communications applications. The MPC8536E is a member of the PowerQUICC<sup>&#174;</sup> III&#8482; family of devices that combine system-level support for industry-standard interfaces with processors that implement Power Architecture technology. None /docs/en/reference-manual/MPC8536ERM.pdf English 14772745 None Reference Manual 2024-12-15 N /docs/en/reference-manual/MPC8536ERM.pdf MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Reference Manual with Updates - Reference Manual /docs/en/reference-manual/MPC8536ERM.pdf documents 500633505221135046 Reference Manual N Y en None Y t877 pdf 1 N N MPC8536E PowerQUICC<sup>&#174;</sup> III Integrated Processor Reference Manual with Updates - Reference Manual 14.8 MB MPC8536ERM N 1224106426497725579696 製品概要 1 /docs/en/product-brief/MPC8536EPB.pdf 2008-09-09 1221013098264726296700 PSP 2 Sep 9, 2008 Product Brief 製品概要 The MPC8536E is a new low-power, high-performance member of the PowerQUICC<sup>&#174;</sup> III&#8482; processor family that combines a computation-intensive super-scalar Power Architecture&#8482; processor core with high-performance system peripherals and advanced power management techniques to deliver high-performance computing in low-power envelopes required for imaging,&#13;&#10;communications, and industrial applications. None /docs/en/product-brief/MPC8536EPB.pdf English 517384 None Product Brief 2022-12-07 /docs/en/product-brief/MPC8536EPB.pdf MPC8536E Product Brief /docs/en/product-brief/MPC8536EPB.pdf documents 899114358132306053 Product Brief N Y en None Y t532 pdf 0 N MPC8536E Product Brief 517.4 KB MPC8536EPB N 1221013098264726296700 true Y Products

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