The PCA9641 is a 2-to-1 I²C controller demultiplexer with an arbiter function. It is designed for high reliability dual controller I²C-bus applications where correct system operation is required, even when two I²C-bus controllers issue their commands at the same time. The arbiter will select a winner and let it work uninterrupted, and the losing controller will take control of the I²C-bus after the winner has finished. The arbiter also allows for queued requests where a controller requests the downstream bus while the other controller has control.
A race condition occurs when two controllers try to access the downstream I²C-bus at almost the same time. The PCA9641 intelligently selects one winning controller and the losing controller gains control of the bus after the winning controller gives up the bus or the reserve time has expired.
Multiple transactions can be done without interruption. The time needed for multiple transactions on the downstream bus can be reserved by programming the Reserve Time register. During the reserve time, the downstream bus cannot be lost.
Software reset allows a controller to send a reset through the I²C-bus to put the PCA9641’s registers into the power-on reset condition.
The Device ID of the PCA9641 can be read by the controller and includes manufacturer, device type and revision.
When there is no activity on the downstream I²C-bus over 100 ms, optionally the PCA9641 will disconnect the downstream bus to both controllers to avoid a lock-up on the I²C-bus.
The interrupt outputs are used to provide an indication of which controller has control of the bus, and which controller has lost the downstream bus. One interrupt input (INT_IN) collects downstream information and propagates it to the two upstream I²C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the controller know if the shared mail box has any new mail or if the outgoing mail has not been read by the other controller. Those interrupts can be disabled and will not generate an interrupt if the masking option is set.
The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9641. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 3.3 V devices without any additional protection.
The PCA9641 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 3.6 V tolerant.
An active LOW reset input allows the PCA9641A to be initialized. Pulling the RESET pin LOW resets the I²C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function.
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クイック・リファレンス ドキュメンテーションの種類.
1-5 の 8 ドキュメント
3 設計・ファイル
完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.