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シンボルおよびフットプリント
PCA9614DP-TSSOP10-CAD Symbol and PCB Footprint – BXL File
Two-Channel Multipoint Fast-Mode Plus Differential I²C-Bus Buffer with Hot-Swap Logic
The PCA9614 is a Fast-mode Plus (Fm+) SMBus/I²C-bus buffer that extends the normal single-ended SMBus/I²C-bus through electrically noisy environments using a differential SMBus/I²C-bus (dI²C) physical layer, which is transparent to the SMBus/I²C-bus protocol layer. It consists of two single-ended to differential driver channels for the SCL (serial clock), SDA (serial data).
The use of differential transmission lines between identical dI²C bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors.
The SMBus/I²C-bus was conceived as a simple slow speed digital link for short runs, typically on a single PCB or between adjacent PCBs with a common ground connection. Applications that extend the bus length or run long cables require careful design to preserve noise margin and reject interference.
The I²C-bus buffers were designed to solve these problems and are ideally suited for rugged high noise environments and/or longer cable applications, allow multiple targets, and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least three meters (3 m), or longer cable runs at lower clock speeds. The dI²C-bus buffers are compatible with existing SMBus/I2C-bus devices and can drive Standard, Fast-mode, and Fast-mode Plus devices on the single-ended side.
Signal direction is automatic and requires no external control. To prevent bus latch-up the I²C-bus side employs static level offset. Take care when connecting the PCA9614 to other SMBus/I²C-bus buffers that do not operate with other static level offset bus buffers.
These devices are a bridge between the normal 2-wire single-ended wired-OR SMBus/I²C-bus and the 4-wire dI²C-bus.
The PCA9614 has two supply voltages, VDD(A) and VDD(B). VDD(A), the card side supply, only serves as a reference and ranges from 2.3 V to 5.5 V. VDD(B), the line side supply, serves as the majority supply for circuitry, and ranges from 3.0 V to 5.5 V.
TSSOP10
製品詳細
Features
System Features
- New dI2C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
- 2 channel dI²C (differential I²C) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL drive capability
- Compatible with I²C-bus Standard/Fast-mode and SMBus, Fast-mode Plus up to 1 MHz
- Active HIGH (internal pull-up resistor) Enable disables devices to high-impedance state
- Single-ended I²C-bus on card side up to 540 pF
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Differential I²C-bus on cable side supporting multi-drop bus
- Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
- dI²C output: 1.5 V differential output with nominal terminals
- Differential line impedance (user defined): 100 Ω nominal suggested
- Receive input sensitivity: ±200 mV
- Hysteresis: ±30 mV typical
- Input impedance: high-impedance (1 MΩ typical)
- Receive input voltage range: ‑0.5 V to +5.5 V
- Lock-up free operation
- Supports arbitration and clock stretching across the dI²C-bus buffers
- Powered-off and powering-up high-impedance I²C-bus pins
- Operating supply voltage (VDD(A)) range of 2.3 V to 5.5 V with single-ended side 5.5 V tolerant
- Differential I²C-bus operating supply voltage (VDD(B)) range of 3.0 V to 5.5 V with 5.5 V tolerant. Best operation is at 5 V.
- ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Package offering: TSSOP10
購入/パラメータ
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