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シンボルおよびフットプリント
PCA9616PW-TSSOP16-CAD Symbol and PCB Footprint – BXL File
Three-Channel Multipoint Fast-Mode Plus Differential I²C-Bus Buffer with Hot-Swap Logic
The PCA9616 is a Fast-mode Plus (Fm+) SMBus/I²C-bus buffer that extends the normal single-ended SMBus/I²C-bus through electrically noisy environments using a differential SMBus/I²C-bus (dI²C) physical layer, which is transparent to the SMBus/I²C-bus protocol layer. It consists of three single-ended to differential driver channels for the SCL (serial clock), SDA (serial data), and a third channel useful for INT or other signaling.
Remark: If the third channel is not used, the INT pin (pin 7 of the TSSOP16 package) should not be left disconnected or ‘floating’ (it may generate incorrect bus signals due to system noise entering this high-impedance node). Tie it to V SS.
The use of differential transmission lines between identical dI²C bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors.
The SMBus/I²C-bus was conceived as a simple slow speed digital link for short runs, typically on a single PCB or between adjacent PCBs with a common ground connection. Applications that extend the bus length or run long cables require careful design to preserve noise margin and reject interference.
The dI²C-bus buffers were designed to solve these problems and are ideally suited for rugged high noise environments and/or longer cable applications, allow multiple targets, and operate at bus speeds up to 1 MHz clock rate. Cables can be extended to at least three meters (3 m), or longer cable runs at lower clock speeds. The dI²C-bus buffers are compatible with existing SMBus/I²C-bus devices and can drive Standard, Fast-mode, and Fast-mode Plus devices on the single-ended side.
Signal direction is automatic, and requires no external control. To prevent bus latch up, the standard SMBus/I²C-bus side of the bus buffer, the PCA9616 employs static offset, care should be taken when connecting these to other SMBus/I²C-bus buffers that may not operate with static offset.
This device is a bridge between the normal 2-wire single-ended wired-OR SMBus/I²C-bus and the 4-wire dI²C-bus.
Additional circuitry allows the PCA9616 to be used for ‘hot swap’ applications, where systems are always on, but require insertion or removal of modules or cards without disruption to existing signals.
The PCA9616 has two supply voltages, V DD(A) and V DD(B). V DD(A), the card side supply, only serves as a reference and ranges from 0.8 V to 5.5 V. V DD(B), the line side supply, serves as the majority supply for circuitry and ranges from 3.0 V to 5.5 V.
製品詳細
ブロック図
Features
System Features
- New dI²C-bus buffers offer improved resistance to system noise and ground offset up to 1⁄2 of supply voltage
- Hot swap (allows insertion or removal of modules or card without disruption to bus data)
- READY signal (PCA9616 output) indicates device is ready from a cold start
- EN signal (PCA9616 input) controls PCA9616 hot swap sequence
- Bus idle detect (PCA9616 internal function) waits for a bus idle condition before connection is made
- 3 channel dI²C (differential I²C-bus) to Fm+ single-ended buffer operating up to 1 MHz with 30 mA SDA/SCL > 2.2 V, or 3 mA SDA/SCL < 2.4 V
- Compatible with I²C-bus Standard/Fast-mode and Fast-mode Plus at 1 MHz
- Active HIGH (internal pull-up resistor) Enable disables the device to high-impedance state
- Single-ended I²C-bus on card side up to 540 pF >2.2 V and 400 pF <2.4 V
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Differential I²C-bus on cable side supporting multi-drop bus:
- Maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency)
- dI²C output: 1.5 V differential output with nominal terminals
- Differential line impedance (user defined): 100 Ω nominal suggested
- Receive input sensitivity: ±200 mV
- Hysteresis: ±30 mV typical
- Input impedance: high-impedance (200 kΩ typical)
- Receive input voltage range: −0.5 V to +5.5 V
- Lock-up free operation
- Supports arbitration and clock stretching across the dI²C-bus buffers
- Powered-off and powering-up high-impedance I²C-bus pins
- Operating supply voltage (V DD(A)) range of 0.8 V to 5.5 V with single-ended side 5.5 V tolerant
- Differential I²C-bus operating supply voltage (V DD(B)) range of 3.0 V to 5.5 V with 5.5 V tolerant. Best operation is at 5 V
- ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Package offering: TSSOP16
購入/パラメータ
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