LPC43S50FET256|Arm Cortex-M4/M0|32-bit MCU

LPC43S50FET256|Arm Cortex-M4/M0|32-bit MCU | NXP Semiconductors

The LPC43S50FET256 is a Arm Cortex-M4 based microcontroller for embedded applications which includes an Arm Cortex-M0 coprocessor, 264 kB of SRAM, security features with AES engine, advanced configurable peripherals such as the State Configurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. The LPC43S50FET256 operates at CPU frequencies of up to 204 MHz.

The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core.

The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set and reduced code size. In LPC43Sx0, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier.

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データ・シート

アプリケーション・ノート

製品詳細

Features

Cortex-M4 Processor core
- Arm Cortex-M4 processor, running at frequencies of up to 204 MHz.
- Built-in Memory Protection Unit (MPU) supporting eight regions.
- Built-in Nested Vectored Interrupt Controller (NVIC).
- Hardware floating-point unit making the core a Cortex-M4.
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
Cortex-M0 Processor core
- Arm Cortex-M0 coprocessor capable of off-loading the main Arm Cortex-M4F application processor.
- Running at frequencies of up to 204 MHz.
- JTAG
- Built-in NVIC.
On-chip memory
- 264 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually
- 64 kB ROM containing boot code and on-chip software drivers.
- 64 bit general-purpose OTP memory
- Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key storage One bank can store an encrypted key for decoding the boot image.
AES engine for encryption and decryption of the boot image and data with DMA support and programmable via a ROM-based API.
Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % accuracy over temperature and voltage.
- Ultra-low power Real-Time Clock (RTC) crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Clock output.
Configurable digital peripherals
- Serial GPIO (SGPIO) interface.
- State Configurable Timer (SCTimer/PWM) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0).
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY (USB1).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
- One SPI controller.
- One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to 1 Mbit/s.
- One standard I²C-bus interface with monitor mode and with standard I/O pins.
- Two I²S interfaces, each with DMA support and with one input and one output.
Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
- LCD controller with DMA support and a programmable display resolution of up to 1024 H x 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB followers
- Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- One motor control Pulse Width Modulator (PWM) for three-phase motor control.
- One Quadrature Encoder Interface (QEI).
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer (WWDT).
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
- Alarm timer; can be battery powered.
Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
Unique ID for each device.
Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
- Available as LBGA256 package.

Target Applications

Communication hubs
Automotive aftermarket
Power management
Consumer health devices
Embedded audio applications
Industrial control
Industrial automation
White goods

パーツ説明を表示	注文	コンピュータ支援設計モデル	動作周波数[最大](MHz)	汎用I/O	USB Controllers	USB (speed)	USB (type)	CAN	UART	I²C	SPI	ADCチャンネル	ADCビット	ADC	SCTimer / PWM	パッケージタイプ	電源電圧 [最小] (V)	電源電圧 [最大] (V)	状況	製品カテゴリー
LPC43S50FET256 データ・シート			204	164	2	HS (2x)	host/device	2	4	2	3	2	10	400 ksps	1	LBGA256	2.2	3.6	アクティブ	190-LPC4300-

設計・リソース

デザイン・ファイル

クイック・リファレンス設計・ファイルの種類.

4 設計・ファイル

シミュレーションとモデル
IBIS models for LPC18x0 and LPC43x0 FBD208

ZIP改訂 2Mar 25, 2020377.1 KBIBIS_LPC18x0_LPC43x0FBD208
ダウンロードToggle Dropdown
- キューに追加
- キューから削除
- ファイルサイズが大きい場合にお勧めします。
- キューを表示
シミュレーションとモデル
BSDL for LPC18xx and LPC43xx

ZIP改訂 2Feb 27, 2018269.0 KBBSDL_LPC18XX_43XX

アカウントが必要です
ダウンロードToggle Dropdown
- キューに追加
- キューから削除
- ファイルサイズが大きい場合にお勧めします。
- キューを表示
シンボルおよびフットプリント
LPC43xx/LPC18xx Eagle symbols

ZIP改訂 0Jun 3, 201614.9 KBLPC43XX-EAGLE-SYM

アカウントが必要です
ダウンロードToggle Dropdown
- キューに追加
- キューから削除
- ファイルサイズが大きい場合にお勧めします。
- キューを表示
シンボルおよびフットプリント
LPC18XX_43XX_SCH Orcad Symbols

ZIP改訂 1.0Apr 30, 201852.2 KBLPC18XX_43XX_SCH_1

アカウントが必要です
ダウンロードToggle Dropdown
- キューに追加
- キューから削除
- ファイルサイズが大きい場合にお勧めします。
- キューを表示

ハードウェア

クイック・リファレンスボードタイプ.

1-5 の 6 ハードウェア提供

エミュレータ、プローブ、プログラマ
Universal Multilink開発インターフェース

UMultilink
エミュレータ、プローブ、プログラマ
PEmicro Cyclone programmer

CYCLONE
エミュレータ、プローブ、プログラマ
PEmicro Cyclone FX programmer

CYCLONE-FX
追加ハードウェアを利用可能パートナー・ソリューションの特集を表示.
エミュレータ、プローブ、プログラマ
Universal Multilink FX高速開発インターフェース

U-MULTILINK-FX
評価・開発ボード
LPCXpresso43S67 Development Board

OM13084
評価・開発ボード
MPC5646C Devlce and Target Adapters

MPC5646C-DB

全て表示

ショッピング・カート

32-Bit Arm® Cortex®-M4/M0 Flashless MCU with Security Features; 264 KB SRAM; Ethernet; Two HS USBs; LCD

製品詳細

Features

Target Applications

アプリケーション

インダストリアル

オートモーティブ

コンスーマ

購入/パラメータ

ドキュメント

絞り込み

アプリケーション・ノート (15)

USBD Library for LPC4300/LPC1800 series MCUs[TN00041]

Connecting TFT LCD with LCD controller of LPC MCU[AN12027]

LPC18S/43S00, LPC18/4300 Random Number Generator[AN11643]

SCTimer/PWM cookbook[AN11538]

LPC18Sxx/43Sxx Secure Boot from QSPI Device[AN11648]

LPC18Sxx/43Sxx Hardware Versus Software AES Benchmark[AN11649]

Code Read Protection in LPC1800 and LPC4300[AN11581]

Implementing PWM dithering on the LPC18xx SCTimer/PWM[AN11580]

SCT camera interface design with LPC1800 and LPC4300[AN11365]

AES encryption and decryption software on LPC microcontrollers[AN11241]

SDRAM interface to LPC18xx/43xx EMC[AN11508]

Implementing a UART using SGPIO on LPC4300[AN11351]

SGPIO camera module design using LPC4300[AN11343]

How to implement the PMBus software stack[AN11318]

UUencoding for UART ISP[AN11229]

エラッタ (1)

Errata sheet LPC43S50, LPC43S30, LPC43S20[ES_LPC43SX0]

サポート情報 (1)

Connecting a USB power switch to the LPC18xx / LPC43xx[TN00007]

データ・シート (1)

32-bit Arm® Cortex®-M4/M0 flashless MCU with security features; up to 264 kB SRAM, Ethernet; two HS USBs, AES engine, LCD, EMC, SPIFI[LPC43S50_30_20]

パッケージ情報 (1)

plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm[SOT740-2]

ファクト・シート (1)

LPC43Sxx Series of MCUs - Fact Sheet[LPC43SXXLF]

ユーザ・ガイド (2)

LPC43xx/LPC43Sxx Arm® Cortex®-M4/M0 multi-core microcontroller[UM10503]

LPC18xx Arm® Cortex®-M3 microcontroller[UM10430]

レポートまたはプレゼンテーション (1)

Driving LPC1700/LPC1800/LPC4300 with EPSON Crystals[R_10076]

絞り込み

アプリケーション・ノート (15)

USBD Library for LPC4300/LPC1800 series MCUs[TN00041]

Connecting TFT LCD with LCD controller of LPC MCU[AN12027]

LPC18S/43S00, LPC18/4300 Random Number Generator[AN11643]

SCTimer/PWM cookbook[AN11538]

LPC18Sxx/43Sxx Secure Boot from QSPI Device[AN11648]

LPC18Sxx/43Sxx Hardware Versus Software AES Benchmark[AN11649]

Code Read Protection in LPC1800 and LPC4300[AN11581]

Implementing PWM dithering on the LPC18xx SCTimer/PWM[AN11580]

SCT camera interface design with LPC1800 and LPC4300[AN11365]

AES encryption and decryption software on LPC microcontrollers[AN11241]

SDRAM interface to LPC18xx/43xx EMC[AN11508]

Implementing a UART using SGPIO on LPC4300[AN11351]

SGPIO camera module design using LPC4300[AN11343]

How to implement the PMBus software stack[AN11318]

UUencoding for UART ISP[AN11229]

エラッタ (1)

Errata sheet LPC43S50, LPC43S30, LPC43S20[ES_LPC43SX0]

サポート情報 (1)

Connecting a USB power switch to the LPC18xx / LPC43xx[TN00007]

データ・シート (1)

32-bit Arm® Cortex®-M4/M0 flashless MCU with security features; up to 264 kB SRAM, Ethernet; two HS USBs, AES engine, LCD, EMC, SPIFI[LPC43S50_30_20]

パッケージ情報 (1)

plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm[SOT740-2]

ファクト・シート (1)

LPC43Sxx Series of MCUs - Fact Sheet[LPC43SXXLF]

ユーザ・ガイド (2)

LPC43xx/LPC43Sxx Arm® Cortex®-M4/M0 multi-core microcontroller[UM10503]

LPC18xx Arm® Cortex®-M3 microcontroller[UM10430]

レポートまたはプレゼンテーション (1)

Driving LPC1700/LPC1800/LPC4300 with EPSON Crystals[R_10076]

設計・リソース

デザイン・ファイル

絞り込み

32-Bit Arm^® Cortex^®-M4/M0 Flashless MCU with Security Features; 264 KB SRAM; Ethernet; Two HS USBs; LCD

32-bit Arm^® Cortex^®-M4/M0 flashless MCU with security features; up to 264 kB SRAM, Ethernet; two HS USBs, AES engine, LCD, EMC, SPIFI[LPC43S50_30_20]

LPC18xx Arm^® Cortex^®-M3 microcontroller[UM10430]

32-bit Arm^® Cortex^®-M4/M0 flashless MCU with security features; up to 264 kB SRAM, Ethernet; two HS USBs, AES engine, LCD, EMC, SPIFI[LPC43S50_30_20]

LPC18xx Arm^® Cortex^®-M3 microcontroller[UM10430]