Layerscape® LX2162A, LX2122A, LX2082A Processors | NXP Semiconductors

Layerscape® LX2162A, LX2122A, LX2082A Processors

From Simply Smart to Truly Intelligent: Edge Computing with i.MX and Layerscape Processors Enables Future Technology

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ブロック図

Layerscape LX2162A Block Diagram

Layerscape LX2162A Block Diagram

Features

  • 16-64-bit Armv8 Cortex-A72 CPU cores, running up to 2.0 GHz
  • 16 MB cache
  • 12 SerDes lanes, operating up to 25 GHz
  • Up to 12 Ethernet ports
  • Supported Ethernet speeds include 1, 2.5, 10, 25, 40 and 50 Gbit/s
  • 105 Gbit/s Layer 2 Ethernet switch
  • Up to 12 PCIe Gen3 lanes, supporting three ports, as wide as x8
  • 50 Gbit/s security accelerator
  • 88 Gbit/s data compression/decompression engine
  • Package: 23x23mm, 1150 pins
  • DDR4 72b including ECC, to 2900 MT/s, maximum capacity of 32 GB

比較表

Layerscape LX2162A Family Members

LX2162A LX2122A LX2082A
Cores 16 12 8
L2 cache 8MB 6MB 8MB
SerDes 12 lanes at up to 25 GHz
PCIe® 3 x Gen3, max width of x8
DDR DDR4, 2900 MT/s, 32 GB capacity
Platform cache + PEB 10MB
Ethernet 105 Gbit/s L2 switch, supporting combinations of 12 ports of 1, 2.5, 10, 25, 40 and 50 Gbit Ethernet
Security 50 Gbit/s
Data Compression Engine 88 Gbit/s
Package 23 x 23 mm, 1150 pins

購入/パラメータ










































































































N true 0 PSPLX2162Aja 24 アプリケーション・ノート Application Note t789 18 エラッタ Errata t522 1 データ・シート Data Sheet t520 1 ファクト・シート Fact Sheet t523 1 リファレンス・マニュアル Reference Manual t877 3 ja ja ja データ・シート Data Sheet 1 1 1 English The Layerscape LX2162A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. 1612518617848698306771 PSP 2.3 MB Registration without Disclaimer None documents Extended 1612518617848698306771 /secured/assets/documents/en/data-sheet/LX2162A.pdf 2324881 /secured/assets/documents/en/data-sheet/LX2162A.pdf LX2162A documents Y N 2021-02-05 Layerscape LX2162A/LX2122A/LX2082A Data Sheet /webapp/Download?colCode=LX2162A&lang_cd=ja /secured/assets/documents/en/data-sheet/LX2162A.pdf Data Sheet N 980000996212993340 2022-12-07 pdf Y en Aug 24, 2021 980000996212993340 Data Sheet Y N Layerscape LX2162A/LX2122A/LX2082A Data Sheet リファレンス・マニュアル Reference Manual 3 2 1 English The QorIQ LX2162A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. 1612510968620707889855 PSP 56.4 MB Registration without Disclaimer None documents Extended 1612510968620707889855 /secured/assets/documents/en/reference-manual/LX2162ARM.pdf 56360053 /secured/assets/documents/en/reference-manual/LX2162ARM.pdf LX2162ARM documents Y N 2021-02-05 LX2162A Reference Manual /webapp/Download?colCode=LX2162ARM&lang_cd=ja /secured/assets/documents/en/reference-manual/LX2162ARM.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Dec 14, 2021 500633505221135046 Reference Manual Y N LX2162A Reference Manual 3 0 English SEC is the chip's cryptographic acceleration and offloading hardware and combines cryptographic and other mathematical functions to create a modular and scalable hardware acceleration and assurance engine. 1595230028328718283020 PSP 6.7 MB Registration without Disclaimer None documents Extended 1595230028328718283020 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf 6704086 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf LX2160ASECRM documents Y N 2020-07-20 LX2160A Security (SEC) Reference Manual /webapp/Download?colCode=LX2160ASECRM&lang_cd=ja /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 20, 2020 500633505221135046 Reference Manual Y N LX2160A Security (SEC) Reference Manual 4 0 English This document provides information about NXP's second generation Data Path Acceleration Architecture (DPAA2). 1592476874355717141786 PSP 13.9 MB Registration without Disclaimer None documents Extended 1592476874355717141786 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf 13931706 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf LX2160ADPAA2RM documents Y N 2020-06-18 LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual /webapp/Download?colCode=LX2160ADPAA2RM&lang_cd=ja /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 18, 2020 500633505221135046 Reference Manual Y N LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual アプリケーション・ノート Application Note 18 5 3 English AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. 1428008859060729157318 PSP 1.1 MB Registration without Disclaimer None documents Extended 1428008859060729157318 /secured/assets/documents/en/application-note/AN5097.pdf 1120906 /secured/assets/documents/en/application-note/AN5097.pdf AN5097 documents Y N 2016-10-31 Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /webapp/Download?colCode=AN5097&lang_cd=ja /secured/assets/documents/en/application-note/AN5097.pdf Application Note N 645036621402383989 2024-12-18 pdf Y en Jul 28, 2023 645036621402383989 Application Note Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 6 1 English AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. 1591185804970704148974 PSP 6.1 MB Registration without Disclaimer None documents Extended 1591185804970704148974 /secured/assets/documents/en/application-note/AN12750.pdf 6058065 /secured/assets/documents/en/application-note/AN12750.pdf AN12750 documents Y N 2020-06-03 Enabling 10GBase-KR on QorIQ Platforms Application Note /webapp/Download?colCode=AN12750&lang_cd=ja /secured/assets/documents/en/application-note/AN12750.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 29, 2022 645036621402383989 Application Note Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 7 0 English appllcation note, AN13684, WRIOP port, WRIOP FIFO depletion, Avoid WRIOP FIFO depletion, 100 Gbps bandwidth configuration, WRIOP 100 Gbps, RECYCLE ports speed change impact, WRIOP FIFO size distribution, WRIOP total FIFO size 1658668288921712850073 PSP 208.4 KB None None documents None 1658668288921712850073 /docs/en/application-note/AN13684.pdf 208437 /docs/en/application-note/AN13684.pdf AN13684 documents N N 2022-07-24 Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms /docs/en/application-note/AN13684.pdf /docs/en/application-note/AN13684.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Jul 5, 2022 645036621402383989 Application Note Y N Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms 8 2 English This document provides recommendations for new designs based on the LX2160A and LX2162A, which are advanced, multicore processors that combine 16 Arm® Cortex®-A72 cores with advanced, high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, storage, telecom/datacom, wireless infrastructure, and general-purpose embedded applications. 1611135817359728320834 PSP 1.1 MB Registration without Disclaimer None documents Extended 1611135817359728320834 /secured/assets/documents/en/application-note/AN5407.pdf 1078031 /secured/assets/documents/en/application-note/AN5407.pdf AN5407 documents Y N 2021-01-20 AN5407, LX2160A and LX2162A Design Checklist, Application Note /webapp/Download?colCode=AN5407&lang_cd=ja /secured/assets/documents/en/application-note/AN5407.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 22, 2022 645036621402383989 Application Note Y N AN5407, LX2160A and LX2162A Design Checklist, Application Note 9 0 Chinese 1649067147403724850019zh PSP 155.1 KB None None documents None 1649067147403724850019 /docs/zh/application-note/AN13608.pdf 155124 /docs/zh/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/zh/application-note/AN13608.pdf /docs/zh/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 zh Apr 4, 2022 645036621402383989 Application Note Y N 将Layerscape器件上的FlexTimer串接起来 0 English 1649067147403724850019 PSP 155.1 KB None None documents None 1649067147403724850019 /docs/en/application-note/AN13608.pdf 155124 /docs/en/application-note/AN13608.pdf AN13608 documents N N 2022-04-04 Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf /docs/en/application-note/AN13608.pdf Application Note N 645036621402383989 2023-09-14 pdf N en Apr 4, 2022 645036621402383989 Application Note Y N Chaining FlexTimers on Layerscape Devices 10 4 English AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. 1567589575242748292636 PSP 194.6 KB None None documents None 1567589575242748292636 /docs/en/application-note/AN12572.pdf 194553 /docs/en/application-note/AN12572.pdf AN12572 documents N N 2019-09-04 Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf /docs/en/application-note/AN12572.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 26, 2021 645036621402383989 Application Note Y N Ethernet Backplane Driver Support Application Note 11 0 Chinese The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. 1615209347110741342432zh PSP 194.9 KB None None documents None 1615209347110741342432 /docs/zh/application-note/AN13138.pdf 194894 /docs/zh/application-note/AN13138.pdf AN13138 documents N N 2021-03-08 Xen Deployment on Layerscape Platforms /docs/zh/application-note/AN13138.pdf /docs/zh/application-note/AN13138.pdf Application Note N 645036621402383989 2024-12-13 zh Mar 8, 2021 645036621402383989 Application Note Y N 在Layerscape平台上部署Xen 0 English The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. 1615209347110741342432 PSP 194.9 KB None None documents None 1615209347110741342432 /docs/en/application-note/AN13138.pdf 194894 /docs/en/application-note/AN13138.pdf AN13138 documents N N 2021-03-08 Xen Deployment on Layerscape Platforms /docs/en/application-note/AN13138.pdf /docs/en/application-note/AN13138.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Mar 8, 2021 645036621402383989 Application Note Y N Xen Deployment on Layerscape Platforms 12 0 English application note, AN13031, SDHC, SD card, AC timing with a voltage translator 1612844458694739251362 PSP 230.3 KB None None documents None 1612844458694739251362 /docs/en/application-note/AN13031.pdf 230317 /docs/en/application-note/AN13031.pdf AN13031 documents N N 2021-02-08 Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet /docs/en/application-note/AN13031.pdf /docs/en/application-note/AN13031.pdf Application Note N 645036621402383989 2024-12-13 pdf N en Feb 5, 2021 645036621402383989 Application Note Y N Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet 13 1 English AN12950: This document is intended to serve as a guide to help users configure SerDes equalization settings that are optimal for 25 GbE, 50 GbE, and 100 GbE protocols with an emphasis on tuning transmit equalization parameters. 1600358724323722927383 PSP 848.4 KB None None documents None 1600358724323722927383 /docs/en/application-note/AN12950.pdf 848430 /docs/en/application-note/AN12950.pdf AN12950 documents N N 2020-09-17 Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note /docs/en/application-note/AN12950.pdf /docs/en/application-note/AN12950.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 2, 2020 645036621402383989 Application Note Y N Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note 14 0 Chinese AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ<sup>&#174;</sup> platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105zh PSP 1.0 MB None None documents None 1456317293250700197105 /docs/zh/application-note/AN5260.pdf 1027928 /docs/zh/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/zh/application-note/AN5260.pdf /docs/zh/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 zh Feb 24, 2016 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 1 English AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). 1456317293250700197105 PSP 1.0 MB None None documents None 1456317293250700197105 /docs/en/application-note/AN5260.pdf 1027928 /docs/en/application-note/AN5260.pdf AN5260 documents N N 2016-10-31 PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf /docs/en/application-note/AN5260.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 30, 2020 645036621402383989 Application Note Y N PBL Configuration using QCVS Application Note 15 0 English AN12628: This application note explains how to optimize memory copy routines. 1573117464705697840062 PSP 485.1 KB None None documents None 1573117464705697840062 /docs/en/application-note/AN12628.pdf 485139 /docs/en/application-note/AN12628.pdf AN12628 documents N N 2019-11-07 Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf /docs/en/application-note/AN12628.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 6, 2019 645036621402383989 Application Note Y N Optimizing Memory Copy Routines Application Note 16 1 English Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. 1154542630989715908212 PSP 281.6 KB None None documents None 1154542630989715908212 /docs/en/application-note/AN3300.pdf 281637 /docs/en/application-note/AN3300.pdf AN3300 documents N N 2017-08-17 General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf /docs/en/application-note/AN3300.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 16, 2017 645036621402383989 Application Note Y N General soldering Temperature Process Guidelines 17 0 English This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). 1500359342664720853564 PSP 650.1 KB Registration without Disclaimer None documents Extended 1500359342664720853564 /secured/assets/documents/en/application-note/AN11979.pdf 650083 /secured/assets/documents/en/application-note/AN11979.pdf AN11979 documents Y N 2017-07-17 AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /webapp/Download?colCode=AN11979&lang_cd=ja /secured/assets/documents/en/application-note/AN11979.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jul 18, 2017 645036621402383989 Application Note Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 18 0 English AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. 1450813697769731607959 PSP 922.3 KB Registration without Disclaimer None documents Extended 1450813697769731607959 /secured/assets/documents/en/application-note/AN5199.pdf 922254 /secured/assets/documents/en/application-note/AN5199.pdf AN5199 documents Y N 2016-10-31 AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /webapp/Download?colCode=AN5199&lang_cd=ja /secured/assets/documents/en/application-note/AN5199.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Dec 22, 2015 645036621402383989 Application Note Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 19 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 20 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311&lang_cd=ja /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 21 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939&lang_cd=ja /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 22 0 English This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. 1154542628855726115465 PSP 151.6 KB None None documents None 1154542628855726115465 /docs/en/application-note/AN3298.pdf 151612 /docs/en/application-note/AN3298.pdf AN3298 documents N N 2016-10-31 Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf /docs/en/application-note/AN3298.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Aug 2, 2006 645036621402383989 Application Note Y N Solder Joint Temperature and Package Peak Temperature エラッタ Errata 1 23 kb 3 English The current errata for LX2162A, released Feb 2023, Rev 3. It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. 1645463094478722376289 PSP None None documents None 1645463094478722376289 https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2162A-ERRATA-LINK documents N N N 2022-02-21 LX2162A Errata https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx Y Errata N 155452329886410597 Y 2023-05-23 URL en May 22, 2023 155452329886410597 Errata Y N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2162A Errata URL ファクト・シート Fact Sheet 1 24 2 English The Layerscape LX2162A processor features 16 Arm®v8 Cortex-A72 cores for server-level Performance in a tiny 23 x 23 mm package. 1599670268085712824312 PSP 5.7 MB None None documents None 1599670268085712824312 /docs/en/fact-sheet/LX2162AFS.pdf 5675261 /docs/en/fact-sheet/LX2162AFS.pdf LX2162AFS documents N N 2020-09-09 Layerscape<sup>®</sup> LX2162A Communications Processor /docs/en/fact-sheet/LX2162AFS.pdf /docs/en/fact-sheet/LX2162AFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Oct 1, 2020 736675474163315314 Fact Sheet Y N Layerscape<sup>®</sup> LX2162A Communications Processor false 0 LX2162A downloads ja true 1 Y PSP Y Y アプリケーション・ノート 18 /secured/assets/documents/en/application-note/AN5097.pdf 2016-10-31 1428008859060729157318 PSP 5 Jul 28, 2023 Application Note AN5097: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR4 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5097.pdf English documents 1120906 None 645036621402383989 2024-12-18 Y /webapp/Download?colCode=AN5097&lang_cd=ja Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces /secured/assets/documents/en/application-note/AN5097.pdf documents 645036621402383989 Application Note N en Extended Y pdf 3 Y N Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces 1.1 MB AN5097 N 1428008859060729157318 /secured/assets/documents/en/application-note/AN12750.pdf 2020-06-03 1591185804970704148974 PSP 6 Jul 29, 2022 Application Note AN12750: This application note describes 10GBase-KR link training to get optimal training parameters and the procedure to validate it. Registration without Disclaimer /secured/assets/documents/en/application-note/AN12750.pdf English documents 6058065 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN12750&lang_cd=ja Enabling 10GBase-KR on QorIQ Platforms Application Note /secured/assets/documents/en/application-note/AN12750.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N Enabling 10GBase-KR on QorIQ Platforms Application Note 6.1 MB AN12750 N 1591185804970704148974 /docs/en/application-note/AN13684.pdf 2022-07-24 1658668288921712850073 PSP 7 Jul 5, 2022 Application Note appllcation note, AN13684, WRIOP port, WRIOP FIFO depletion, Avoid WRIOP FIFO depletion, 100 Gbps bandwidth configuration, WRIOP 100 Gbps, RECYCLE ports speed change impact, WRIOP FIFO size distribution, WRIOP total FIFO size None /docs/en/application-note/AN13684.pdf English documents 208437 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13684.pdf Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms /docs/en/application-note/AN13684.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Avoiding WRIOP FIFO Depletion for 100 Gbps Bandwidth Configuration on LX2 Platforms 208.4 KB AN13684 N 1658668288921712850073 /secured/assets/documents/en/application-note/AN5407.pdf 2021-01-20 1611135817359728320834 PSP 8 Apr 22, 2022 Application Note This document provides recommendations for new designs based on the LX2160A and LX2162A, which are advanced, multicore processors that combine 16 Arm® Cortex®-A72 cores with advanced, high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, storage, telecom/datacom, wireless infrastructure, and general-purpose embedded applications. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5407.pdf English documents 1078031 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5407&lang_cd=ja AN5407, LX2160A and LX2162A Design Checklist, Application Note /secured/assets/documents/en/application-note/AN5407.pdf documents 645036621402383989 Application Note N en Extended Y pdf 2 Y N AN5407, LX2160A and LX2162A Design Checklist, Application Note 1.1 MB AN5407 N 1611135817359728320834 /docs/en/application-note/AN13608.pdf 2022-04-04 1649067147403724850019 PSP 9 Apr 4, 2022 Application Note None /docs/en/application-note/AN13608.pdf English documents 155124 None 645036621402383989 2023-09-14 N /docs/en/application-note/AN13608.pdf Chaining FlexTimers on Layerscape Devices /docs/en/application-note/AN13608.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Chaining FlexTimers on Layerscape Devices 155.1 KB AN13608 N 1649067147403724850019 /docs/en/application-note/AN12572.pdf 2019-09-04 1567589575242748292636 PSP 10 Nov 26, 2021 Application Note AN12572: This document describes how to enable backplane support for Layerscape and QorIQ devices with embedded support for this type of connection. None /docs/en/application-note/AN12572.pdf English documents 194553 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12572.pdf Ethernet Backplane Driver Support Application Note /docs/en/application-note/AN12572.pdf documents 645036621402383989 Application Note N en None Y pdf 4 N N Ethernet Backplane Driver Support Application Note 194.6 KB AN12572 N 1567589575242748292636 /docs/en/application-note/AN13138.pdf 2021-03-08 1615209347110741342432 PSP 11 Mar 8, 2021 Application Note The intent of this document is to provide the necessary information to hardware, software, and system engineers to run the Xen hypervisor on NXP Layerscape platforms. In this action, we consider basic scenarios, such as basic domain management, dom0less, and device passthrough. None /docs/en/application-note/AN13138.pdf English documents 194894 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13138.pdf Xen Deployment on Layerscape Platforms /docs/en/application-note/AN13138.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Xen Deployment on Layerscape Platforms 194.9 KB AN13138 N 1615209347110741342432 /docs/en/application-note/AN13031.pdf 2021-02-08 1612844458694739251362 PSP 12 Feb 5, 2021 Application Note application note, AN13031, SDHC, SD card, AC timing with a voltage translator None /docs/en/application-note/AN13031.pdf English documents 230317 None 645036621402383989 2024-12-13 N /docs/en/application-note/AN13031.pdf Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet /docs/en/application-note/AN13031.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Recommendations for SD Connections to 1.8 V SDHC Interfaces Data Sheet 230.3 KB AN13031 N 1612844458694739251362 /docs/en/application-note/AN12950.pdf 2020-09-17 1600358724323722927383 PSP 13 Dec 2, 2020 Application Note AN12950: This document is intended to serve as a guide to help users configure SerDes equalization settings that are optimal for 25 GbE, 50 GbE, and 100 GbE protocols with an emphasis on tuning transmit equalization parameters. None /docs/en/application-note/AN12950.pdf English documents 848430 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12950.pdf Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note /docs/en/application-note/AN12950.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N Optimizing Serial Interface Equalization Settings for 25 GbE on LX216xA Processor Application Note 848.4 KB AN12950 N 1600358724323722927383 /docs/en/application-note/AN5260.pdf 2016-10-31 1456317293250700197105 PSP 14 Nov 30, 2020 Application Note AN5260: This document describes the steps required to configure pre-boot loader (PBL) on NXP QorIQ platform using the PBL tool included in QorIQ Configuration and Validation Suite (QCVS). None /docs/en/application-note/AN5260.pdf English documents 1027928 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5260.pdf PBL Configuration using QCVS Application Note /docs/en/application-note/AN5260.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N PBL Configuration using QCVS Application Note 1.0 MB AN5260 N 1456317293250700197105 /docs/en/application-note/AN12628.pdf 2019-11-07 1573117464705697840062 PSP 15 Nov 6, 2019 Application Note AN12628: This application note explains how to optimize memory copy routines. None /docs/en/application-note/AN12628.pdf English documents 485139 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN12628.pdf Optimizing Memory Copy Routines Application Note /docs/en/application-note/AN12628.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Optimizing Memory Copy Routines Application Note 485.1 KB AN12628 N 1573117464705697840062 /docs/en/application-note/AN3300.pdf 2017-08-17 1154542630989715908212 PSP 16 Aug 16, 2017 Application Note Solder joint and package temperature for Pb-free BGA in SnPB and Pb-free solders in IR or convection reflow ovens are discussed in this document. None /docs/en/application-note/AN3300.pdf English documents 281637 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3300.pdf General soldering Temperature Process Guidelines /docs/en/application-note/AN3300.pdf documents 645036621402383989 Application Note N en None Y pdf 1 N N General soldering Temperature Process Guidelines 281.6 KB AN3300 N 1154542630989715908212 /secured/assets/documents/en/application-note/AN11979.pdf 2017-07-17 1500359342664720853564 PSP 17 Jul 18, 2017 Application Note This application note presents configuration and example use cases of L2 switch (DPSW) and Edge Virtual Bridge (DPDMUX). Registration without Disclaimer /secured/assets/documents/en/application-note/AN11979.pdf English documents 650083 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN11979&lang_cd=ja AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note /secured/assets/documents/en/application-note/AN11979.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN11979, DPAA2 Ethernet Switch and Edge Virtual Bridge - Application Note 650.1 KB AN11979 N 1500359342664720853564 /secured/assets/documents/en/application-note/AN5199.pdf 2016-10-31 1450813697769731607959 PSP 18 Dec 22, 2015 Application Note AN5199: This document targets customers familiar with DPAA1 who would like to know more about DPAA2 before migrating to DPAA2 enabled devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN5199.pdf English documents 922254 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN5199&lang_cd=ja AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note /secured/assets/documents/en/application-note/AN5199.pdf documents 645036621402383989 Application Note N en Extended Y pdf 0 Y N AN5199, Key Concepts for the Transition from DPAA1 to DPAA2 - Application Note 922.3 KB AN5199 N 1450813697769731607959 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 19 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 20 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311&lang_cd=ja SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 21 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939&lang_cd=ja DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN3298.pdf 2016-10-31 1154542628855726115465 PSP 22 Aug 2, 2006 Application Note This document demonstrates how to determine the package temperature and thermal mass dependent moisture sensitivity level (MSL) of products to ensure reliable processing of moisture sensitive surface mount components. Comply with these recommendations to maintain package integrity of components during any heat exposure of board soldering and de-soldering. None /docs/en/application-note/AN3298.pdf English documents 151612 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3298.pdf Solder Joint Temperature and Package Peak Temperature /docs/en/application-note/AN3298.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N Solder Joint Temperature and Package Peak Temperature 151.6 KB AN3298 N 1154542628855726115465 エラッタ 1 https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx 2022-02-21 1645463094478722376289 PSP 23 May 22, 2023 Errata The current errata for LX2162A, released Feb 2023, Rev 3. It is an NDA document. Please see the Sharepoint site https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx (NDA and NXP-issued invite required), or contact your NXP representative. URL None https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx English documents kb None 155452329886410597 2023-05-23 N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx LX2162A Errata https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx documents 155452329886410597 Errata N en None Y Y N URL 3 N LX2162A Errata Y LX2162A-ERRATA-LINK N https://nxp1.sharepoint.com/teams/ext204/SitePages/Home.aspx 1645463094478722376289 データ・シート 1 /secured/assets/documents/en/data-sheet/LX2162A.pdf 2021-02-05 1612518617848698306771 PSP 1 Aug 24, 2021 Data Sheet The Layerscape LX2162A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. Registration without Disclaimer /secured/assets/documents/en/data-sheet/LX2162A.pdf English documents 2324881 None 980000996212993340 2022-12-07 Y /webapp/Download?colCode=LX2162A&lang_cd=ja Layerscape LX2162A/LX2122A/LX2082A Data Sheet /secured/assets/documents/en/data-sheet/LX2162A.pdf documents 980000996212993340 Data Sheet N en Extended Y pdf 1 Y N Layerscape LX2162A/LX2122A/LX2082A Data Sheet 2.3 MB LX2162A N 1612518617848698306771 ファクト・シート 1 /docs/en/fact-sheet/LX2162AFS.pdf 2020-09-09 1599670268085712824312 PSP 24 Oct 1, 2020 Fact Sheet The Layerscape LX2162A processor features 16 Arm®v8 Cortex-A72 cores for server-level Performance in a tiny 23 x 23 mm package. None /docs/en/fact-sheet/LX2162AFS.pdf English documents 5675261 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/LX2162AFS.pdf Layerscape<sup>®</sup> LX2162A Communications Processor /docs/en/fact-sheet/LX2162AFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 2 N N Layerscape<sup>®</sup> LX2162A Communications Processor 5.7 MB LX2162AFS N 1599670268085712824312 リファレンス・マニュアル 3 /secured/assets/documents/en/reference-manual/LX2162ARM.pdf 2021-02-05 1612510968620707889855 PSP 2 Dec 14, 2021 Reference Manual The QorIQ LX2162A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks. Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2162ARM.pdf English documents 56360053 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=LX2162ARM&lang_cd=ja LX2162A Reference Manual /secured/assets/documents/en/reference-manual/LX2162ARM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N LX2162A Reference Manual 56.4 MB LX2162ARM N 1612510968620707889855 /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf 2020-07-20 1595230028328718283020 PSP 3 Jul 20, 2020 Reference Manual SEC is the chip's cryptographic acceleration and offloading hardware and combines cryptographic and other mathematical functions to create a modular and scalable hardware acceleration and assurance engine. Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf English documents 6704086 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=LX2160ASECRM&lang_cd=ja LX2160A Security (SEC) Reference Manual /secured/assets/documents/en/reference-manual/LX2160ASECRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N LX2160A Security (SEC) Reference Manual 6.7 MB LX2160ASECRM N 1595230028328718283020 /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf 2020-06-18 1592476874355717141786 PSP 4 Jun 18, 2020 Reference Manual This document provides information about NXP's second generation Data Path Acceleration Architecture (DPAA2). Registration without Disclaimer /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf English documents 13931706 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=LX2160ADPAA2RM&lang_cd=ja LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual /secured/assets/documents/en/reference-manual/LX2160ADPAA2RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N LX2160A Family Data Path Acceleration Architecture, Second Generation (DPAA2) Low-Level Hardware Reference Manual 13.9 MB LX2160ADPAA2RM N 1592476874355717141786 true Y Products

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