Multi-Output DC-DC Regulator for Low Power LS1 Communication Processors
デザイン・ファイル
完全な内訳を受け取ります。 製品の設置面積などについては、 eCad ファイル.
Layerscape® 1024A Dual-Core Processor
LS1024A multicore devices are not recommended for new designs. Please use LS1023A devices.
The LS1024A multicore communications processors delivers scalability, superior packet handling capabilities, vastly increased VPN and SSL throughput and optimized quality of service hardware features. For broadband home routers, VoIP gateways, IoT (Internet of Things) gateways, and low-end network attached storage.
Based on single- or dual-core Arm® Cortex®-A9 CPU cores, the LS1024A of system-on-chip (SoC) processor achieves the lowest power consumption in its class (<3 W typical at 900 MHz) to provide performance scalability and maximum flexibility. In addition to high throughput IPSec and SSL CPU offload with an onboard security engine that includes a powerful deep packet inspection engine with GZIP decompression capability. The LS1024A processor includes SATA-2 interfaces, along with a powerful processing engine and integrated RAID controller to provide an ideal solution for network attached storage applications.
The LS1024A OpenWRT Linux-based SDK is optimized for both single- and dual-core operation.
Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.
製品詳細
ブロック図
Features
Core Complex
- Single or dual Arm Cortex-A9 SMP/AMP 32-bit cores, with NEON DSP and FPU, up to 1.2 GHz
- 32 KB instruction and data caches
- 256 KB shared L2 cache
Networking Elements
- Three Gigabit Ethernet controllers supporting 3x RGMII or 2x RMII and 1x SGMII
- Twin PCIe Gen2 controllers
- Two SATA2 controllers with RAID 0/1/5
- SerDes 3 lanes at up to 5 GHz
- USB3.0 controller with PHY
Accelerators and Memory Control
- DDR memory controller supports DDR3 at up to 1066 MHz
- 16-bit, 32-bit memory supported
- Packet Processing and Forwarding Engine (PPFE)
- Delivers 2Gbps of PPPoE/NAT routing with 64B packets
- HW QoS compliant to HGI2.0 on all data interfaces
- TCP offload engine
- Security engine
- Full IPSec offload including SNOW and Kasumi
- Full SSL offload
- Deep Packet Inspection Engine
- Antivirus
- Application-specific QoS
- Advanced Diagnostics
- Telephony Functions
- DECT baseband CAT-iq 2.0 compliant, upgradeable to 2.1 and 3.0
- TDM support for wideband voice
Basic Peripherals and Interconnect
- AMBA AXI/AHB crossbar
- Integrated Flash controller
- USB2.0 controller with PHY supporting OTG, Host and Device modes
- 1x I²C
- 2x SPI
- 2x UART
- 1x I2S
- TDM
比較表
| LS1024A | |
|---|---|
| Cores | 2x Arm Cortex-A9 |
| Top Core Frequency | 1.2 GHz |
| L2 Size | 256 KB |
| DDR 2/3 Support | 16/32-bit |
| GE Ports | 3 |
| Serdes | 3 |
| PCI Express Controllers | 2 |
| SATA-2 Ports | 2 |
| USB Ports | 1x USB2.0 1x USB3.0 |
| Accelerators | SE, PPFE, DPIE, DECT |
LS1024A Development Tools
- Software
- Application Solution Kit
- Development Software
- Hardware
- Reference Designs
- Emulators/Probes
- Support
関連製品
低オーミック4極双投アナログ・スイッチ
USB PDおよびType-C電流制限電源スイッチ
Bidirectional High-Side Power Switch for Charger and USB‑OTG Combined Applications
3.3 V, Two Differential Channel, 2-1 Multiplexer/Demultiplexer Switch
Dual-Supply Translating Transceiver (Open-Drain, Auto-Direction Sensing)
Bidirectional Voltage Level Translator for Open-Drain and Push-Pull Applications
SMBus対応の8ピン・リモート/ローカル・デジタル温度センサ
High-Speed USB 2.0 Switch with Enable
購入/パラメータ
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ドキュメント
クイック・リファレンス ドキュメンテーションの種類.
1-5 の 13 ドキュメント
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アプリケーション・ノート
PBL Configuration using QCVS Application Note
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アプリケーション・ノート
General soldering Temperature Process Guidelines
設計・リソース
ハードウェア
クイック・リファレンス
ボードタイプ.
4 ハードウェア提供
-
評価・開発ボードLayerscape LS1024A Reference Design Board注目
-
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エミュレータ、プローブ、プログラマLS Processor Probe Tips for CodeWarrior TAP
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追加ハードウェアを利用可能 パートナー・ソリューションの特集を表示.
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エミュレータ、プローブ、プログラマCodeWarrior® TAP
ソフトウェア
クイック・リファレンス ソフトウェア・タイプ.
3 ソフトウェア・ファイル
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ライブラリ
EAR2 ASK Loadable binaries for LS1024A
注: より快適にご利用いただくために、ソフトウェアのダウンロードはデスクトップで行うことを推奨します。
トレーニング
2 トレーニング